Functional Testing of Semiconductor Random Access Memories. - Magdy S. Abadir; Hassan K. Reghbati (ACM Comput. Surv., 1983)

LSI Testing Techniques. - Magdy S. Abadir; Hassan K. Reghbati (IEEE Micro, 1983)

Test generation for LSI: A case study. - Magdy S. Abadir; Hassan K. Reghbati (DAC, 1984)

Functional Test Generation for LSI Circuits Described by Binary Decision Diagrams. - Magdy S. Abadir; Hassan K. Reghbati (ITC, 1985)

A Knowledge-Based System for Designing Testable VLSI Chips. - Magdy S. Abadir; Melvin A. Breuer (IEEE Des. Test, 1985)

Scan Path with Look Ahead Shifting (SPLASH). - Magdy S. Abadir; Melvin A. Breuer (ITC, 1986)

Test Schedules for VLSI Circuits Having Built-In Test Hardware. - Magdy S. Abadir; Melvin A. Breuer (IEEE Trans. Computers, 1986)

Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams. - Magdy S. Abadir; Hassan K. Reghbati (IEEE Trans. Computers, 1986)

Logic design verification via test generation. - Magdy S. Abadir; Jack Ferguson; Tom E. Kirkland (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

TIGER: testability insertion guidance expert system. - Magdy S. Abadir (ICCAD, 1989)

An improved layout verification algorithm (LAVA). - Magdy S. Abadir; Jack Ferguson (EURO-DAC, 1990)

Partitioning Hierarchical Designs for Testability. - Magdy S. Abadir; Joe Newman; Desmond D'Souza; Steve Spencer (ITC, 1991)

Automatic Test Knowledge Extraction from VHDL (ATKET). - Praveen Vishakantaiah; Jacob A. Abraham; Magdy S. Abadir (DAC, 1992)

AMBIANT: Automatic Generation of Behavioral Modifications for Testability. - Praveen Vishakantaiah; Thomas Thomas; Jacob A. Abraham; Magdy S. Abadir (ICCD, 1993)

Efficient Algorithmic Circuit Verification Using Indexed BDDs. - James R. Bitner; Jawahar Jain; Magdy S. Abadir; Jacob A. Abraham; Donald S. Fussell (FTCS, 1994)

Analyzing Multichip Module Testing Strategies. - Magdy S. Abadir; Ashish R. Parikh; Linda Bal; Peter Sandborn; Ken Drake (IEEE Des. Test Comput., 1994)

Introduction. - Magdy S. Abadir; Tony Ambler (J. Electron. Test., 1994)

High Level Test Economics Advisor (Hi-TEA). - Magdy S. Abadir; Ashish Parikh; Linda Bal; Peter Sandborn; Cynthia F. Murphy (J. Electron. Test., 1994)

Multichip systems trade-off analysis tool. - Peter Sandborn; Rajarshi Ghosh; Ken Drake; Magdy S. Abadir; Linda Bal; Ashish Parikh (J. Electron. Test., 1994)

PowerPCTM Array Verification Methodology using Formal Techniques. - Neeta Ganguly; Magdy S. Abadir; Manish Pandey (ITC, 1996)

Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation. - Manish Pandey; Richard Raimi; Randal E. Bryant; Magdy S. Abadir (DAC, 1997)

A New Validation Methodology Combining Test and Formal Verification for PowerPCTM Microprocessor Arrays. - Li-C. Wang; Magdy S. Abadir (ITC, 1997)

Microprocessor Test and Validation: Any New Avenues? - Magdy S. Abadir; Jacob A. Abraham; Hong Hao; C. Hunter; Wayne M. Needham; Ron G. Walther (VTS, 1997)

Cost-Driven Ranking of Memory Elements for Partial Intrusion. - Magdy S. Abadir; Rohit Kapur (IEEE Des. Test Comput., 1997)

Design and Test Economics-An Extra Dimension. - Tony Ambler; Magdy S. Abadir (IEEE Des. Test Comput., 1997)

Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die. - Cynthia F. Murphy; Magdy S. Abadir; Peter Sandborn (J. Electron. Test., 1997)

Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. - Jawahar Jain; James R. Bitner; Magdy S. Abadir; Jacob A. Abraham; Donald S. Fussell (IEEE Trans. Computers, 1997)

Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation. - Li-C. Wang; Magdy S. Abadir; Nari Krishnamurthy (DAC, 1998)

Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. - Li-C. Wang; Magdy S. Abadir; Jing Zeng (DATE, 1998)

Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors. - Arun Chandra; Li-C. Wang; Magdy S. Abadir (Great Lakes Symposium on VLSI, 1998)

On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays. - Li-C. Wang; Magdy S. Abadir; Jing Zeng (VTS, 1998)

Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays. - Li-C. Wang; Magdy S. Abadir (J. Electron. Test., 1998)

On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays. - Li-C. Wang; Magdy S. Abadir; Jing Zeng (ACM Trans. Design Autom. Electr. Syst., 1998)

Design-for-test methodology for Motorola PowerPC microprocessors. - Magdy S. Abadir; Rajesh Raina (ITC, 1999)

Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors. - Li-C. Wang; Magdy S. Abadir (ITC, 1999)

Experience in Validation of PowerPCTM Microprocessor Embedded Arrays. - Li-C. Wang; Magdy S. Abadir (J. Electron. Test., 1999)

A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPCTM microprocessor. - Jayanta Bhadra; Magdy S. Abadir; Jacob A. Abraham (CICC, 2000)

A Quick and Inexpensive Method to Identify False Critical Paths Using ATPG Techniques: an Experiment with a PowerPC Microprocessor. - Jayanta Batra; Magdy S. Abadir; Jacob A. Abraham (LATW, 2000)

Design Optimization Based on Diagnosis Techniques. - Andreas G. Veneris; Magdy S. Abadir; Ibrahim N. Haji (LATW, 2000)

Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. - Narayanan Krishnamurthy; Andrew K. Martin; Magdy S. Abadir; Jacob A. Abraham (VTS, 2000)

Guest Editors' Introduction: Microprocessor Test and Verification. - Magdy S. Abadir; Sumit Dasgupta (IEEE Des. Test Comput., 2000)

Validating PowerPC Microprocessor Custom Memories. - Narayanan Krishnamurthy; Andrew K. Martin; Magdy S. Abadir; Jacob A. Abraham (IEEE Des. Test Comput., 2000)

Guest Editorial. - Magdy S. Abadir (J. Electron. Test., 2000)

On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors. - Li-C. Wang; Magdy S. Abadir (J. Electron. Test., 2000)

Oscillation Ring Delay Test for High Performance Microprocessors. - Wen Ching Wu; Chung-Len Lee 001; Ming Shae Wu; Jwu E. Chen; Magdy S. Abadir (J. Electron. Test., 2000)

Design rewiring based on diagnosis techniques. - Andreas G. Veneris; Magdy S. Abadir; Ivor Ting (ASP-DAC, 2001)

Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation. - Jayanta Bhadra; Andrew K. Martin; Jacob A. Abraham; Magdy S. Abadir (CHARME, 2001)

Full chip false timing path identification: applications to the PowerPCTM microprocessors. - Jing Zeng; Magdy S. Abadir; Jayanta Bhadra; Jacob A. Abraham (DATE, 2001)

A language formalism for verification of PowerPCTM custom memories using compositions of abstract specifications. - Jayanta Bhadra; Andrew K. Martin; Jacob A. Abraham; Magdy S. Abadir (HLDVT, 2001)

Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. - Mrinal Bose; Elizabeth M. Rudnick; Magdy S. Abadir (IOLTW, 2001)

Verification and Validation of Complex Digital Systems: An Industrial Perspective. - Magdy S. Abadir; Li-C. Wang (ISQED, 2001)

ATPG Driven Logic Synthesis for Delay and Power Minimization. - Ivor Ting; Andreas G. Veneris; Magdy S. Abadir (LATW, 2001)

ATPG for Design Errors-Is It Possible? - Magdy S. Abadir; Scott Davidson 001; Vijay Nagasamy; Dhiraj K. Pradhan; Prab Varma (VTS, 2001)

Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor. - Magdy S. Abadir; Juhong Zhu; Li-C. Wang (VTS, 2001)

Very Low Cost Testers: Opportunities and Challenges. - Jay Bedsole; Rajesh Raina; Al Crouch; Magdy S. Abadir (IEEE Des. Test Comput., 2001)

Design and Development Paradigm for Industrial Formal Verification CAD Tools. - Narayanan Krishnamurthy; Magdy S. Abadir; Andrew K. Martin; Jacob A. Abraham (IEEE Des. Test Comput., 2001)

False timing path identification using ATPG techniques and delay-based information. - Jing Zeng; Magdy S. Abadir; Jacob A. Abraham (DAC, 2002)

Minimal Test for Coupling Faults in Word-Oriented Memories. - Ad J. van de Goor; Magdy S. Abadir; Alan Carlin (DATE, 2002)

Incremental Diagnosis and Correction of Multiple Faults and Errors. - Andreas G. Veneris; Jiang Brandon Liu; Mandana Amiri; Magdy S. Abadir (DATE, 2002)

Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. - Ganapathy Parthasarathy; Madhu K. Iyer; Tao Feng 012; Li-C. Wang; Kwang-Ting Cheng; Magdy S. Abadir (ITC, 2002)

Design Rewiring Using ATPG. - Andreas G. Veneris; Magdy S. Abadir; Mandana Amiri (ITC, 2002)

On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults. - Li-C. Wang; Magdy S. Abadir; Juhong Zhu (ITC, 2002)

Efficient and Exact Diagnosis of Multiple Stuck-At Faults. - Jiang Brandon Liu; Andreas G. Veneris; Magdy S. Abadir (LATW, 2002)

Validation and Verification of Complex Digital Systems: A Practical Perspective. - Li-C. Wang; Magdy S. Abadir (LATW, 2002)

Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? - Narayanan Krishnamurthy; Jayanta Bhadra; Magdy S. Abadir; Jacob A. Abraham (VTS, 2002)

Design rewiring using ATPG. - Andreas G. Veneris; Magdy S. Abadir (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Enhanced symbolic simulation for efficient verification of embedded array systems. - Tao Feng 012; Li-C. Wang; Kwang-Ting Cheng; Manish Pandey; Magdy S. Abadir (ASP-DAC, 2003)

An automated method for test model generation from switch level circuits. - Tim McDougall; Atanas N. Parashkevov; Simon Jolly; Juhong Zhu; Jing Zeng; Carol Pyron; Magdy S. Abadir (ASP-DAC, 2003)

Logic verification based on diagnosis techniques. - Andreas G. Veneris; Alexander Smith 001; Magdy S. Abadir (ASP-DAC, 2003)

Automated Test Model Generation from Switch Level Custom Circuits. - Magdy S. Abadir; Jing Zeng; Carol Pyron; Juhong Zhu (Asian Test Symposium, 2003)

Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. - Angela Krstic; Li-C. Wang; Kwang-Ting Cheng; Jing-Jia Liou; Magdy S. Abadir (DATE, 2003)

IDAP: A Tool for High Level Power Estimation of Custom Array Structures. - Mahesh Mamidipaka; Kamal S. Khouri; Nikil D. Dutt; Magdy S. Abadir (ICCAD, 2003)

Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. - Li-C. Wang; Angela Krstic; Leonard Lee; Kwang-Ting Cheng; M. Ray Mercer; Thomas W. Williams; Magdy S. Abadir (ITC, 2003)

A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. - Jayanta Bhadra; Narayanan Krishnamurthy; Magdy S. Abadir (MTV, 2003)

Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs. - Magdy S. Abadir; Juhong Zhu (VTS, 2003)

Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems. - Li-C. Wang; Tao Feng 012; Kwang-Ting (Tim) Cheng; Magdy S. Abadir; Manish Pandey (Des. Autom. Embed. Syst., 2003)

Formal Verification Successes at Motorola. - Magdy S. Abadir; Ken Albin; John Havlicek; Narayanan Krishnamurthy; Andrew K. Martin (Formal Methods Syst. Des., 2003)

Analytical models for leakage power estimation of memory array structures. - Mahesh Mamidipaka; Kamal S. Khouri; Nikil D. Dutt; Magdy S. Abadir (CODES+ISSS, 2004)

On path-based learning and its applications in delay test and diagnosis. - Li-C. Wang; T. M. Mak; Kwang-Ting Cheng; Magdy S. Abadir (DAC, 2004)

Debugging sequential circuits using Boolean satisfiability. - Moayad Fahim Ali; Andreas G. Veneris; Alexander Smith 001; Sean Safarpour; Rolf Drechsler; Magdy S. Abadir (ICCAD, 2004)

Fault equivalence and diagnostic test generation using ATPG. - Andreas G. Veneris; Robert Chang; Magdy S. Abadir; Mandana Amiri (ISCAS (5), 2004)

On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. - Jing Zeng; Magdy S. Abadir; A. Kolhatkar; G. Vandling; Li-C. Wang; Jacob A. Abraham (ITC, 2004)

Identification of Gates for Covering all Critical Paths. - M. Moiz Khan; Spyros Tragoudas; Magdy S. Abadir; Jiang Brandon Liu (MTV, 2004)

On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. - Jing Zeng; Magdy S. Abadir; G. Vandling; Li-C. Wang; S. Karako; Jacob A. Abraham (MTV, 2004)

Towards The Complete Elimination of Gate/Switch Level Simulations. - Narayanan Krishnamurthy; Jayanta Bhadra; Magdy S. Abadir; Jacob A. Abraham (VLSI Design, 2004)

Guest Editors' Introduction: The Verification and Test of Complex Digital ICs. - Magdy S. Abadir; Li-C. Wang (IEEE Des. Test Comput., 2004)

Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. - Jayanta Bhadra; Narayanan Krishnamurthy; Magdy S. Abadir (IEEE Des. Test Comput., 2004)

A Top-Down Methodology for Microprocessor Validation. - Prabhat Mishra 001; Nikil D. Dutt; Narayanan Krishnamurthy; Magdy S. Abadir (IEEE Des. Test Comput., 2004)

Choosing flows and methodologies for SoC design. - Dennis Wassung; Yervant Zorian; Magdy S. Abadir; Mark Bapst; Colin Harris (DAC, 2005)

Diagnosing multiple transition faults in the absence of timing information. - Jiang Brandon Liu; Magdy S. Abadir; Andreas G. Veneris; Sean Safarpour (ACM Great Lakes Symposium on VLSI, 2005)

Establishing latch correspondence for embedded circuits of PowerPC microprocessors. - Himyanshu Anand; Jayanta Bhadra; Alper Sen 001; Magdy S. Abadir; Kenneth G. Davis (HLDVT, 2005)

Post-verification debugging of hierarchical designs. - Moayad Fahim Ali; Sean Safarpour; Andreas G. Veneris; Magdy S. Abadir; Rolf Drechsler (ICCAD, 2005)

Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects. - Benjamin N. Lee; Hui Li; Li-C. Wang; Magdy S. Abadir (ITC, 2005)

Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. - Jayanta Bhadra; Magdy S. Abadir; David Burgess; Ekaterina Trofimova (MTV, 2005)

Retiming Verification Using Sequential Equivalence Checking. - Brian Kahne; Magdy S. Abadir (MTV, 2005)

Recent Advances in Verification, Equivalence Checking and SAT-Solvers. - Dhiraj K. Pradhan; Magdy S. Abadir; Mauricio Varea (VLSI Design, 2005)

Reducing Pattern Delay Variations for Screening Frequency Dependent Defects. - Benjamin N. Lee; Li-C. Wang; Magdy S. Abadir (VTS, 2005)

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. - Andreas G. Veneris; Robert Chang; Magdy S. Abadir; Sep Seyedi (J. Electron. Test., 2005)

A methodology for validation of microprocessors using symbolic simulation. - Prabhat Mishra 001; Nikil D. Dutt; Narayanan Krishnamurthy; Magdy S. Abadir (Int. J. Embed. Syst., 2005)

Floorplan driven leakage power aware IP-based SoC design space exploration. - Aseem Gupta; Nikil D. Dutt; Fadi J. Kurdahi; Kamal S. Khouri; Magdy S. Abadir (CODES+ISSS, 2006)

Refined statistical static timing analysis through. - Benjamin N. Lee; Li-C. Wang; Magdy S. Abadir (DAC, 2006)

Extracting a simplified view of design functionality via vector simulation. - Onur Guzey; Charles H.-P. Wen; Li-C. Wang; Tao Feng 012; Magdy S. Abadir (HLDVT, 2006)

Extracting a Simplified View of Design Functionality Based on Vector Simulation. - Onur Guzey; Charles H.-P. Wen; Li-C. Wang; Tao Feng 012; Hillel Miller; Magdy S. Abadir (Haifa Verification Conference, 2006)

Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs. - Magdy S. Abadir (IOLTS, 2006)

Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective. - Benjamin N. Lee; Li-C. Wang; Magdy S. Abadir (ITC, 2006)

Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. - Heon-Mo Koo; Prabhat Mishra 001; Jayanta Bhadra; Magdy S. Abadir (MTV, 2006)

A Trace-Driven Validation Methodology for Multi-Processor SOCS. - Jayanta Bhadra; Ekaterina Trofimova; Leonard J. Giordano; Magdy S. Abadir (SoCC, 2006)

LEAF: A System Level Leakage-Aware Floorplanner for SoCs. - Aseem Gupta; Nikil D. Dutt; Fadi J. Kurdahi; Kamal S. Khouri; Magdy S. Abadir (ASP-DAC, 2007)

Design-Silicon Timing Correlation A Data Mining Perspective. - Li-C. Wang; Pouria Bastani; Magdy S. Abadir (DAC, 2007)

Maximum circuit activity estimation using pseudo-boolean satisfiability. - Hratch Mangassarian; Andreas G. Veneris; Sean Safarpour; Farid N. Najm; Magdy S. Abadir (DATE, 2007)

Analyzing the risk of timing modeling based on path delay tests. - Pouria Bastani; Benjamin N. Lee; Li-C. Wang; Savithri Sundareswaran; Magdy S. Abadir (ITC, 2007)

Statistical analysis and optimization of parametric delay test. - Sean Hsi Yuan Wu; Benjamin N. Lee; Li-C. Wang; Magdy S. Abadir (ITC, 2007)

STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. - Aseem Gupta; Nikil D. Dutt; Fadi J. Kurdahi; Kamal S. Khouri; Magdy S. Abadir (VLSI Design, 2007)

Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. - Jayanta Bhadra; Magdy S. Abadir; Li-C. Wang (IEEE Des. Test Comput., 2007)

A Survey of Hybrid Techniques for Functional Verification. - Jayanta Bhadra; Magdy S. Abadir; Li-C. Wang; Sandip Ray (IEEE Des. Test Comput., 2007)

Statistical diagnosis of unmodeled systematic timing effects. - Pouria Bastani; Nicholas Callegari; Li-C. Wang; Magdy S. Abadir (DAC, 2008)

Predictive runtime verification of multi-processor SoCs in SystemC. - Alper Sen 001; Vinit Ogale; Magdy S. Abadir (DAC, 2008)

Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. - Aseem Gupta; Nikil D. Dutt; Fadi J. Kurdahi; Kamal S. Khouri; Magdy S. Abadir (ISQED, 2008)

Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained. - Pouria Bastani; Nicholas Callegari; Li-C. Wang; Magdy S. Abadir (ITC, 2008)

Linking Statistical Learning to Diagnosis. - Pouria Bastani; Li-C. Wang; Magdy S. Abadir (IEEE Des. Test Comput., 2008)

Validating Power ArchitectureTM Technology-Based MPSoCs Through Executable Specifications. - Jayanta Bhadra; Ekaterina Trofimova; Magdy S. Abadir (IEEE Trans. Very Large Scale Integr. Syst., 2008)

TRAM: A tool for Temperature and Reliability Aware Memory Design. - Amin Khajeh; Aseem Gupta; Nikil D. Dutt; Fadi J. Kurdahi; Ahmed M. Eltawil; Kamal S. Khouri; Magdy S. Abadir (DATE, 2009)

Minimizing outlier delay test cost in the presence of systematic variability. - Dragoljub Gagi Drmanac; Brendon Bolin; Li-C. Wang; Magdy S. Abadir (ITC, 2009)

A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch. - Nicholas Callegari; Pouria Bastani; Li-C. Wang; Magdy S. Abadir (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch. - Nicholas Callegari; Dragoljub Gagi Drmanac; Li-C. Wang; Magdy S. Abadir (DAC, 2010)

Coverage metrics for verification of concurrent SystemC designs using mutation testing. - Alper Sen 001; Magdy S. Abadir (HLDVT, 2010)

Design for reality: knowledge discovery in design and test data. - Magdy S. Abadir (SBCCI, 2010)

Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch. - Pouria Bastani; Nicholas Callegari; Li-C. Wang; Magdy S. Abadir (IEEE Des. Test Comput., 2010)

Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits. - Dragoljub Gagi Drmanac; Nik Sumikawa; LeRoy Winemberg; Li-C. Wang; Magdy S. Abadir (DATE, 2011)

Forward prediction based on wafer sort data - A case study. - Nik Sumikawa; Dragoljub Gagi Drmanac; Li-C. Wang; LeRoy Winemberg; Magdy S. Abadir (ITC, 2011)

Understanding customer returns from a test perspective. - Nik Sumikawa; Dragoljub Gagi Drmanac; Li-C. Wang; LeRoy Winemberg; Magdy S. Abadir (VTS, 2011)

Novel test detection to improve simulation efficiency - A commercial experiment. - Wen Chen 016; Nik Sumikawa; Li-C. Wang; Jayanta Bhadra; Xiushan Feng; Magdy S. Abadir (ICCAD, 2012)

Screening customer returns with multivariate test analysis. - Nik Sumikawa; Jeff Tikkanen; Li-C. Wang; LeRoy Winemberg; Magdy S. Abadir (ITC, 2012)

An experiment of burn-in time reduction based on parametric test analysis. - Nik Sumikawa; Li-C. Wang; Magdy S. Abadir (ITC, 2012)

Data mining based prediction paradigm and its applications in design automation. - Magdy S. Abadir; Nik Sumikawa; Wen Chen 016; Li-C. Wang (VLSI-DAT, 2012)

Introduction to special section on verification challenges in the concurrent world. - Sandip Ray; Jayanta Bhadra; Magdy S. Abadir; Li-C. Wang; Aarti Gupta (ACM Trans. Design Autom. Electr. Syst., 2012)

Simulation knowledge extraction and reuse in constrained random processor verification. - Wen Chen 016; Li-C. Wang; Jay Bhadra; Magdy S. Abadir (DAC, 2013)

A pattern mining framework for inter-wafer abnormality analysis. - Nik Sumikawa; Li-C. Wang; Magdy S. Abadir (ITC, 2013)

Novel test analysis to improve structural coverage - A commercial experiment. - Wen Chen 016; Li-C. Wang; Jayanta Bhadra; Magdy S. Abadir (VLSI-DAT, 2013)

Keynote 1 - VLSI 2.0: R&D Post Moore. - Sani R. Nassif; Yale N. Patt; Magdy S. Abadir (VLSI-SoC, 2013)

Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs. - Sandip Ray; Jay Bhadra; Magdy S. Abadir; Li-C. Wang (J. Electron. Test., 2013)

Data Mining In EDA - Basic Principles, Promises, and Constraints. - Li-C. Wang; Magdy S. Abadir (DAC, 2014)

Multivariate outlier modeling for capturing customer returns - How simple it can be. - Jeff Tikkanen; Nik Sumikawa; Li-C. Wang; Magdy S. Abadir (IOLTS, 2014)

Yield optimization using advanced statistical correlation methods. - Jeff Tikkanen; Sebastian Siatkowski; Nik Sumikawa; Li-C. Wang; Magdy S. Abadir (ITC, 2014)

Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification. - Magdy S. Abadir; Jayanta Bhadra; Wen Chen 016; Li-C. Wang (IEEE Des. Test, 2017)

Challenges and Trends in Modern SoC Design Verification. - Wen Chen 016; Sandip Ray; Jayanta Bhadra; Magdy S. Abadir; Li-C. Wang (IEEE Des. Test, 2017)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)