Formal derivation of optimal active shielding for low-power on-chip buses. - Maged Ghoneima; Yehea I. Ismail (ICCAD, 2004)

Low power coupling-based encoding for on-chip buses. - Maged Ghoneima; Yehea I. Ismail (ISCAS (2), 2004)

Effect of relative delay on the dissipated energy in coupled interconnects. - Maged Ghoneima; Yehea I. Ismail (ISCAS (2), 2004)

Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. - Maged Ghoneima; Yehea I. Ismail (ISLPED, 2004)

Low-power on-chip bus architecture using dynamic relative delays. - Maged Ghoneima; Yehea I. Ismail (SoCC, 2004)

Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses. - Maged Ghoneima; Yehea I. Ismail (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Low-power prediction based data transfer architecture. - Maged Ghoneima; Ehsan Atoofian; Amirali Baniasadi; Yehea I. Ismail (CICC, 2005)

The importance of including thermal effects in estimating the effectiveness of power reduction techniques. - Ja Chun Ku; Maged Ghoneima; Yehea I. Ismail (CICC, 2005)

Physical limitations on the bit-rate of on-chip interconnects. - Noha H. Mahmoud; Maged Ghoneima; Yehea I. Ismail (ACM Great Lakes Symposium on VLSI, 2005)

A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. - Muhammad M. Khellah; Maged Ghoneima; James W. Tschanz; Yibin Ye; Nasser A. Kurd; Javed Barkatullah; Srikanth Nimmagadda; Yehea I. Ismail (ICCD, 2005)

Accurate decoupling of capacitively coupled buses. - Maged Ghoneima; Yehea I. Ismail (ISCAS (4), 2005)

Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. - Yehea I. Ismail; Muhammad M. Khellah; Maged Ghoneima; James W. Tschanz; Yibin Ye; Vivek De (ISCAS (1), 2005)

Optimum positioning of interleaved repeaters in bidirectional buses. - Maged Ghoneima; Yehea I. Ismail (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Reducing the data switching activity of serialized datastreams. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; Vivek De (ISCAS, 2006)

Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. - Keith A. Bowman; James W. Tschanz; Muhammad M. Khellah; Maged Ghoneima; Yehea I. Ismail; Vivek De (ISLPED, 2006)

Reducing the Data Switching Activity on Serial Link Buses. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; Vivek De (ISQED, 2006)

Formal derivation of optimal active shielding for low-power on-chip buses. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; James W. Tschanz; Vivek De (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; James W. Tschanz; Vivek De (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; Vivek De (VLSI Design, 2007)

Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. - Maged Ghoneima; Muhammad M. Khellah; James W. Tschanz; Yibin Ye; Nasser A. Kurd; Javed Barkatullah; Srikanth Nimmagadda; Yehea I. Ismail; Vivek K. De (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; Vivek De (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Serial-Link Bus: A Low-Power On-Chip Bus Architecture. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; James W. Tschanz; Vivek De (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A novel power gated digitally controlled oscillator. - Amr M. Lotfy; Maged Ghoneima; Mohamed Abdel-Moneum (ICEAC, 2011)

A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients. - Sally Safwat; Maged Ghoneima; Yehea I. Ismail (ICEAC, 2011)

A dynamic calibration scheme for on-chip process and temperature variations. - Mina Raymond; Maged Ghoneima; Yehea I. Ismail (ISCAS, 2011)

A 12Gbps all digital low power SerDes transceiver for on-chip networking. - Sally Safwat; Ezz El-Din O. Hussein; Maged Ghoneima; Yehea I. Ismail (ISCAS, 2011)

Guest Editorial Special Issue on ISCAS 2010. - Maged Ghoneima; Yong Lian 001; Gabriele Manganaro; Shahriar Mirabbasi; Christian Piguet; Wouter A. Serdijn (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Modeling the response of Bang-Bang digital PLLs to phase error perturbations. - Moataz Abdelfattah; Maged Ghoneima; Yehea I. Ismail; Amr Lotfy; Mohamed Abdel-moneum; Nasser A. Kurd; Greg Taylor (CICC, 2012)

A 16Gbps low power self-timed SerDes transceiver for multi-core communication. - Ezz El-Din O. Hussein; Sally Safwat; Maged Ghoneima; Yehea I. Ismail (ISCAS, 2012)

A 0.8V 6.4µW compact mixed-signal front-end for neural implants. - Ahmed El Kholy; Maged Ghoneima; Khaled Sharaf (ISCAS, 2012)

A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter. - Sally Safwat; Amr Lotfy; Maged Ghoneima; Yehea I. Ismail (ISCAS, 2012)

A novel digital loop filter architecture for bang-bang ADPLL. - Moataz Abdelfattah; Maged Ghoneima; Yehea I. Ismail; Amr Lotfy; Mohamed Abdelsalam; Mohamed Abdel-moneum; Nasser A. Kurd; Greg Taylor (SoCC, 2012)

Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks. - Abdelrahman H. Elsayed; Ramy N. Tadros; Maged Ghoneima; Yehea I. Ismail (ISCAS, 2014)

A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks. - Ramy N. Tadros; Abdelrahman H. Elsayed; Maged Ghoneima; Yehea I. Ismail (ISCAS, 2014)

A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme. - Ramy N. Tadros; Ahmed H. Abdelrahman; Maged Ghoneima; Yehea Ismail (ICEAC, 2015)

Structure optimization for efficient AlN piezoelectric energy harvesters. - Mostafa Shadoufa; Ahmed Emad; Maged Ghoneima; Mohamed A. E. Mahmoud; Mohamed Dessouky (ICECS, 2015)

New polynomial basis versatile multiplier over GF(2m) for low-power on-chip crypto-systems. - Mustafa Khairallah; Maged Ghoneima (ISCAS, 2015)

2T2M memristor-based memory cell for higher stability RRAM modules. - Noha Shaarawy; Maged Ghoneima; Ahmed G. Radwan (ISCAS, 2015)

A reference-less multilevel memristor based RRAM module. - Ahmed A. M. Emara; Maged Ghoneima (MWSCAS, 2015)

A fixed function 3D rendering hardware for mobile applications. - Eslam Khafagy; Ahmed Hatab; Amr Rashed; Ahmed A. M. Emara; Maged Ghoneima (ICM, 2016)

Sperm-shaped magnetic microrobots: Fabrication using electrospinning, modeling, and characterization. - Islam S. M. Khalil; Ahmet Fatih Tabak; Abdelrahman Hosney; Abdallah Mohamed; Anke Klingner; Maged Ghoneima; Metin Sitti (ICRA, 2016)

A fast locking hybrid TDC-BB ADPLL utilizing proportional derivative digital loop filter and power gated DCO. - Amr Lotfy; Maged Ghoneima; Mohamed Abdel-Moneum (ISCAS, 2016)

Modeling and analysis of stretching strain in clamped-clamped beams for energy harvesting. - Ahmed Emad; Mohamed A. E. Mahmoud; Maged Ghoneima; Mohamed Dessouky (MWSCAS, 2016)

Optimization of the output power of a frequency-up conversion piezoelectric energy harvester. - Mostafa Shadoufa; Mohamed Mahmoud; Maged Ghoneima; Mohamed Dessouky (MWSCAS, 2016)

Tile-Based Modular Architecture for Accelerating Homomorphic Function Evaluation on FPGA. - Mustafa Khairallah; Maged Ghoneima (IACR Cryptol. ePrint Arch., 2016)

Metaheuristic optimization in path planning of autonomous vehicles under the ATOM framework. - Youmna Magdy; Omar M. Shehata; Mohamed Abdelaziz; Maged Ghoneima; Farid A. Tolbah (ICVES, 2017)

PASSIOT: A Pareto-optimal multi-objective optimization approach for synthesis of analog circuits using Sobol' indices-based engine. - Taher Kourany; Maged Ghoneima; Emad Hegazi; Yehea Ismail (Integr., 2017)

Pyramidal Neuron Architectures for AcceleratingDeep Neural Networks on FPGA. - Hossam O. Ahmed; Maged Ghoneima; Mohamed Dessouky (AHS, 2018)

Real-Time Car Detection-Based Depth Estimation Using Mono Camera. - I. Mohamed Elzayat; M. Ahmed Saad; M. Mohamed Mostafa; R. Mahmoud Hassan; Hossam Abd El Munim; Maged Ghoneima; M. Saeed Darweesh; Hassan Mostafa (ICM, 2018)

High-Speed 2D Parallel MAC Unit Hardware Accelerator for Convolutional Neural Network. - Hossam O. Ahmed; Maged Ghoneima; Mohamed Dessouky (IntelliSys (1), 2018)

Real-Time Lane Detection-Based Line Segment Detection. - Ahmed Mahmoud; Loay Ehab; Mohamed Reda; Mostafa Abdelaleem; Hossam Abd El Munim; Maged Ghoneima; M. Saeed Darweesh; Hassan Mostafa (NGCAS, 2018)

Design and analysis of 2T2M hybrid CMOS-Memristor based RRAM. - Noha Shaarawy; Ahmed A. M. Emara; Ahmed M. El-Naggar; Mohammed E. Elbtity; Maged Ghoneima; Ahmed G. Radwan (Microelectron. J., 2018)

Systolic-based pyramidal neuron accelerator blocks for convolutional neural network. - Hossam O. Ahmed; Maged Ghoneima; Mohamed Dessouky (Microelectron. J., 2019)

Reconfigurable Systolic-based Pyramidal Neuron Block for CNN Acceleration on FPGA. - Hossam O. Ahmed; Maged Ghoneima; Mohamed Dessouky (ICSET, 2020)