An Efficient Twin-Precision Multiplier. - Magnus Själander; Henrik Eriksson; Per Larsson-Edefors (ICCD, 2004)

A low-leakage twin-precision multiplier using reconfigurable power gating. - Magnus Själander; Mindaugas Drazdziulis; Per Larsson-Edefors; Henrik Eriksson (ISCAS (2), 2005)

Multiplier reduction tree with logarithmic logic depth and regular connectivity. - Henrik Eriksson; Per Larsson-Edefors; Mary Sheeran; Magnus Själander; Daniel Johansson; Martin Scholin (ISCAS, 2006)

A Flexible Datapath Interconnect for Embedded Applications. - Magnus Själander; Per Larsson-Edefors; Magnus Björk (ISVLSI, 2007)

A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures. - Magnus Själander; Andrei Sergeevich Terechko; Marc Duranton (DSD, 2008)

High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree. - Magnus Själander; Per Larsson-Edefors (ICECS, 2008)

Early detection and bypassing of trivial operations to improve energy efficiency of processors. - Md. Mafijul Islam; Magnus Själander; Per Stenström (Microprocess. Microsystems, 2008)

A Flexible Code Compression Scheme Using Partitioned Look-Up Tables. - Martin Thuresson; Magnus Själander; Per Stenström (HiPEAC, 2009)

Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree. - Patrik Kimfors; Niklas Broman; Andreas Haraldsson; Kasyab P. Subramaniyan; Magnus Själander; Henrik Eriksson; Per Larsson-Edefors (ICECS, 2009)

Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements. - Tung Thanh Hoang; Magnus Själander; Per Larsson-Edefors (IPDPS, 2009)

Scheduling for an Embedded Architecture with a Flexible Datapath. - Thomas Schilling; Magnus Själander; Per Larsson-Edefors (ISVLSI, 2009)

High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture. - Tung Thanh Hoang; Magnus Själander; Per Larsson-Edefors (SoCC, 2009)

Multiplication Acceleration Through Twin Precision. - Magnus Själander; Per Larsson-Edefors (IEEE Trans. Very Large Scale Integr. Syst., 2009)

FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. - Martin Thuresson; Magnus Själander; Magnus Björk; Lars J. Svensson; Per Larsson-Edefors; Per Stenström (J. Signal Process. Syst., 2009)

Design space exploration for an embedded processor with flexible datapath interconnect. - Tung Thanh Hoang; Ulf Jalmbrant; Erik der Hagopian; Kasyab P. Subramaniyan; Magnus Själander; Per Larsson-Edefors (ASAP, 2010)

A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit. - Tung Thanh Hoang; Magnus Själander; Per Larsson-Edefors (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Reconfigurable Instruction Decoding for a Wide-Control-Word Processor. - Alen Bardizbanyan; Magnus Själander; Per Larsson-Edefors (IPDPS Workshops, 2011)

Power-Aware Resource Scheduling in Base Stations. - Magnus Själander; Sally A. McKee; Bhavishya Goel; Peter Brauer; David Engdal; András Vajda (MASCOTS, 2011)

Viterbi Accelerator for Embedded Processor Datapaths. - Muhammad Waqar Azhar; Magnus Själander; Hasan Ali; Akshay Vijayashekar; Tung Thanh Hoang; Kashan Khurshid Ansari; Per Larsson-Edefors (ASAP, 2012)

An LTE Uplink Receiver PHY benchmark and subframe-based power management. - Magnus Själander; Sally A. McKee; Peter Brauer; David Engdal; András Vajda (ISPASS, 2012)

Configurable RTL model for level-1 caches. - Vahid Saljooghi; Alen Bardizbanyan; Magnus Själander; Per Larsson-Edefors (NORCHIP, 2012)

Techniques to Measure, Model, and Manage Power. - Bhavishya Goel; Sally A. McKee; Magnus Själander (Adv. Comput., 2012)

Improving data access efficiency by using a tagless access buffer (TAB). - Alen Bardizbanyan; Peter Gavin; David B. Whalley; Magnus Själander; Per Larsson-Edefors; Sally A. McKee; Per Stenström (CGO, 2013)

Speculative tag access for reduced energy dissipation in set-associative L1 data caches. - Alen Bardizbanyan; Magnus Själander; David B. Whalley; Per Larsson-Edefors (ICCD, 2013)

Improving processor efficiency by statically pipelining instructions. - Ian Finlayson; Brandon Davis; Peter Gavin; Gang-Ryung Uh; David B. Whalley; Magnus Själander; Gary S. Tyson (LCTES, 2013)

FlexCore: Implementing an exposed datapath processor. - Magnus Själander; Per Larsson-Edefors (ICSAMOS, 2013)

Designing a practical data filter cache to improve both energy efficiency and performance. - Alen Bardizbanyan; Magnus Själander; David B. Whalley; Per Larsson-Edefors (ACM Trans. Archit. Code Optim., 2013)

Reducing instruction fetch energy in multi-issue processors. - Peter Gavin; David B. Whalley; Magnus Själander (ACM Trans. Archit. Code Optim., 2013)

Reducing set-associative L1 data cache energy by early load data dependence detection (ELD3). - Alen Bardizbanyan; Magnus Själander; David B. Whalley; Per Larsson-Edefors (DATE, 2014)

A tunable cache for approximate computing. - Magnus Själander; Nina Shariati Nilsson; Stefanos Kaxiras (NANOARCH, 2014)

Power-Efficient Computer Architectures: Recent Advances - Magnus Själander; Margaret Martonosi; Stefanos Kaxiras (Power-Efficient Computer Architectures, 2014)

Scheduling instruction effects for a statically pipelined processor. - B. Davis; Ryan Baird; Peter Gavin; Magnus Själander; Ian Finlayson; F. Rasapour; G. Cook; Gang-Ryung Uh; David B. Whalley; Gary S. Tyson (CASES, 2015)

Optimizing Transfers of Control in the Static Pipeline Architecture. - Ryan Baird; Peter Gavin; Magnus Själander; David B. Whalley; Gang-Ryung Uh (LCTES, 2015)

Improving Data Access Efficiency by Using Context-Aware Loads and Stores. - Alen Bardizbanyan; Magnus Själander; David B. Whalley; Per Larsson-Edefors (LCTES, 2015)

Redesigning a tagless access buffer to require minimal ISA changes. - Carlos Sanchez; Peter Gavin; Daniel Moreau; Magnus Själander; David B. Whalley; Per Larsson-Edefors; Sally A. McKee (CASES, 2016)

Techniques for modulating error resilience in emerging multi-value technologies. - Magnus Själander; Gustaf Borgström; Mykhailo V. Klymenko; Françoise Remacle; Stefanos Kaxiras (Conf. Computing Frontiers, 2016)

Practical way halting by speculatively accessing halt tags. - Daniel Moreau; Alen Bardizbanyan; Magnus Själander; David B. Whalley; Per Larsson-Edefors (DATE, 2016)

Poster: Approximation: A New Paradigm also for Wireless Sensing. - Thiemo Voigt; Magnus Själander; Frederik Hermans (EWSN, 2016)

Clairvoyance: look-ahead compile-time scheduling. - Kim-Anh Tran; Trevor E. Carlson; Konstantinos Koukos; Magnus Själander; Vasileios Spiliopoulos 001; Stefanos Kaxiras; Alexandra Jimborean (CGO, 2017)

Transcending Hardware Limits with Software Out-of-Order Processing. - Trevor E. Carlson; Kim-Anh Tran; Alexandra Jimborean; Konstantinos Koukos; Magnus Själander; Stefanos Kaxiras (IEEE Comput. Archit. Lett., 2017)

BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing. - Yaman Umuroglu; Lahiru Rasnayake; Magnus Själander (FPL, 2018)

SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order cores. - Kim-Anh Tran; Alexandra Jimborean; Trevor E. Carlson; Konstantinos Koukos; Magnus Själander; Stefanos Kaxiras (PLDI, 2018)

Static Instruction Scheduling for High Performance on Limited Hardware. - Kim-Anh Tran; Trevor E. Carlson; Konstantinos Koukos; Magnus Själander; Vasileios Spiliopoulos 001; Stefanos Kaxiras; Alexandra Jimborean (IEEE Trans. Computers, 2018)

Ghost loads: what is the cost of invisible speculation? - Christos Sakalis; Mehdi Alipour; Alberto Ros 001; Alexandra Jimborean; Stefanos Kaxiras; Magnus Själander (CF, 2019)

Improving Memory Access Locality for Vectorized Bit-Serial Matrix Multiplication in Reconfigurable Computing. - Lahiru Rasnayake; Magnus Själander (FPT, 2019)

Efficient invisible speculative execution through selective delay and value prediction. - Christos Sakalis; Stefanos Kaxiras; Alberto Ros 001; Alexandra Jimborean; Magnus Själander (ISCA, 2019)

RVSDG: An Intermediate Representation for Optimizing Compilers. - Nico Reissmann; Jan Christian Meyer; Helge Bahmann; Magnus Själander (CoRR, 2019)

EPIC: An Energy-Efficient, High-Performance GPGPU Computing Research Infrastructure. - Magnus Själander; Magnus Jahre; Gunnar Tufte; Nico Reissmann (CoRR, 2019)

Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing. - Yaman Umuroglu; Davide Conficconi; Lahiru Rasnayake; Thomas B. Preußer; Magnus Själander (ACM Trans. Reconfigurable Technol. Syst., 2019)

Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design. - Kim-Anh Tran; Christos Sakalis; Magnus Själander; Alberto Ros 001; Stefanos Kaxiras; Alexandra Jimborean (PACT, 2020)

RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress. - Shounak Chakraborty 001; Sangeet Saha; Magnus Själander; Klaus D. McDonald-Maier (CODES+ISSS, 2020)

Twig: Multi-Agent Task Management for Colocated Latency-Critical Cloud Services. - Rajiv Nishtala; Vinicius Petrucci; Paul M. Carpenter; Magnus Själander (HPCA, 2020)

Evaluating the Potential Applications of Quaternary Logic for Approximate Computing. - Christos Sakalis; Alexandra Jimborean; Stefanos Kaxiras; Magnus Själander (ACM J. Emerg. Technol. Comput. Syst., 2020)

Understanding Selective Delay as a Method for Efficient Secure Speculative Execution. - Christos Sakalis; Stefanos Kaxiras; Alberto Ros 001; Alexandra Jimborean; Magnus Själander (IEEE Trans. Computers, 2020)

Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation. - Christos Sakalis; Zamshed I. Chowdhury; Shayne Wadle; Ismail Akturk; Alberto Ros 001; Magnus Själander; Stefanos Kaxiras; Ulya R. Karpuzcu (SEED, 2021)

Seeds of SEED: Preventing Priority Inversion in Instruction Scheduling to Disrupt Speculative Interference. - Christos Sakalis; Magnus Själander; Stefanos Kaxiras (SEED, 2021)

Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions. - Pavlos Aimoniotis; Christos Sakalis; Magnus Själander; Stefanos Kaxiras (IEEE Comput. Archit. Lett., 2021)

On Value Recomputation to Accelerate Invisible Speculation. - Christos Sakalis; Zamshed I. Chowdhury; Shayne Wadle; Ismail Akturk; Alberto Ros 001; Magnus Själander; Stefanos Kaxiras; Ulya R. Karpuzcu (CoRR, 2021)

Selectively Delaying Instructions to Prevent Microarchitectural Replay Attacks. - Christos Sakalis; Stefanos Kaxiras; Magnus Själander (CoRR, 2021)

"It's a Trap!"-How Speculation Invariance Can Be Abused with Forward Speculative Interference. - Pavlos Aimoniotis; Christos Sakalis; Magnus Själander; Stefanos Kaxiras (CoRR, 2021)

WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption. - Shounak Chakraborty 001; Magnus Själander (ACM Trans. Archit. Code Optim., 2021)

Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization. - Shounak Chakraborty 001; Sangeet Saha; Magnus Själander; Klaus D. McDonald-Maier (ACM Trans. Embed. Comput. Syst., 2021)

STIFF: thermally safe temperature effect inversion aware FinFET based multi-core. - Shounak Chakraborty 001; Vassos Soteriou; Magnus Själander (CF, 2022)

Data-Out Instruction-In (DOIN!): Leveraging Inclusive Caches to Attack Speculative Delay Schemes. - Pavlos Aimoniotis; Amund Bergland Kvalsvik; Magnus Själander; Stefanos Kaxiras (SEED, 2022)

Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR). - Sukarn Agarwal; Shounak Chakraborty 001; Magnus Själander (DAC, 2023)

Doppelganger Loads: A Safe, Complexity-Effective Optimization for Secure Speculation Schemes. - Amund Bergland Kvalsvik; Pavlos Aimoniotis; Stefanos Kaxiras; Magnus Själander (ISCA, 2023)

ReCon: Efficient Detection, Management, and Use of Non-Speculative Information Leakage. - Pavlos Aimoniotis; Amund Bergland Kvalsvik; Xiaoyue Chen; Magnus Själander; Stefanos Kaxiras (MICRO, 2023)

DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore. - Sangeet Saha; Shounak Chakraborty 001; Sukarn Agarwal; Rahul Gangopadhyay; Magnus Själander; Klaus D. McDonald-Maier (IEEE Trans. Parallel Distributed Syst., 2023)

Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks. - Christos Sakalis; Stefanos Kaxiras; Magnus Själander (ACM Trans. Archit. Code Optim., 2023)

BISDU: A Bit-Serial Dot-Product Unit for Microcontrollers. - David Metz 001; Vineet Kumar 002; Magnus Själander (ACM Trans. Embed. Comput. Syst., 2023)

MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing. - Shounak Chakraborty 001; Sangeet Saha; Magnus Själander; Klaus D. McDonald-Maier (DAC, 2024)

R-HLS: An IR for Dynamic High-Level Synthesis and Memory Disambiguation based on Regions and State Edges. - David Metz 001; Nico Reissmann; Magnus Själander (ICCAD, 2024)

Sustainable High-Performance Instruction Selection for Superscalar Processors. - Saeideh Sheikhpour; David Metz 001; Erling Jellum; Magnus Själander; Lieven Eeckhout (ICCAD, 2024)

TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture. - Sukarn Agarwal; Shounak Chakraborty 001; Magnus Själander (IPDPS, 2024)

CATBench: A Compiler Autotuning Benchmarking Suite for Black-box Optimization. - Jacob O. Tørring; Carl Hvarfner; Luigi Nardi; Magnus Själander (CoRR, 2024)

ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment. - Sangeet Saha; Shounak Chakraborty 001; Sukarn Agarwal; Magnus Själander; Klaus D. McDonald-Maier (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Optimizing Energy Efficiency in Subthreshold RISC-V Cores. - Asbjørn Djupdal; Magnus Själander; Magnus Jahre; Snorre Aunet; Trond Ytterdal (CoRR, 2025)

ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes. - Amund Bergland Kvalsvik; Magnus Själander (CoRR, 2025)