A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL. - Vijay Khawshe; Pravin V. Kumar; Renu Rangnekar; Kapil Vyas; Kashi Prabu; Mahabaleshwara; Manish Jain; Navin K. Mishra; Abhijit Abhyankar (VLSI Design, 2007)

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. - Amir Amirkhany; Jason Wei; Navin K. Mishra; Jie Shen 010; Wendemagegnehu T. Beyene; Catherine Chen 005; T. J. Chin; Deborah Dressler; Charlie Huang; Vijay P. Gadde; Mohammad Hekmat; Kambiz Kaviani; et al. (IEEE J. Solid State Circuits, 2012)

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. - Kambiz Kaviani; Ting Wu 003; Jason Wei; Amir Amirkhany; Jie Shen 010; T. J. Chin; Chintan Thakkar; Wendemagegnehu T. Beyene; Norman Chan; Catherine Chen 005; Bing Ren Chuang; Deborah Dressler; et al. (IEEE J. Solid State Circuits, 2012)