PLL Based High Speed Functional Testing. - Jayasanker Jayabalan; Kiang Goh Chee; Ban-Leong Ooi; Mook Seng Leong; Mahadevan K. Iyer; Andrew A. O. Tay (Asian Test Symposium, 2003)

Development of process modeling methodology for flip chip on flex interconnections with non-conductive adhesives. - Xiaowu Zhang; Ee-Hua Wong; Ranjan Rajoo; Mahadevan K. Iyer; J. F. J. M. Caers; X. J. Zhao (Microelectron. Reliab., 2005)