HW/SW co-design architecture exploration for VLSI maze routing. - Mahdi Elghazali; Ahmed Elhossini; Shawki Areibi (CCECE, 2009)

A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology. - Mahdi Elghazali; Manoj Sachdev; Ajoy Opal (CICC, 2014)

A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications. - Mahdi Elghazali; Manoj Sachdev; Ajoy Opal (NEWCAS, 2014)

A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology. - Mahdi Elghazali; Manoj Sachdev; Ajoy Opal (ISVLSI, 2016)

An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technology. - Mahdi Elghazali; Manoj Sachdev; Ajoy Opal (ISQED, 2018)