Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style. - Tooraj Nikoubin; Mahdieh Grailoo; Sayyed Hasan Mozafari (J. Low Power Electron., 2010)

Power and Energy Efficient Standard Cells with CDM Logic Style for Optimization of Multiplier Structures. - Mahdieh Grailoo; Ashish Joshi; Mounika Mulkalapally; Tooraj Nikoubin (ICCCNT, 2016)

UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications. - Mahdieh Grailoo; Bijan Alizadeh; Behjat Forouzandeh (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology. - Tooraj Nikoubin; Mahdieh Grailoo; Changzhi Li (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Improved Range Analysis in Fixed-Point Polynomial Data-Path. - Mahdieh Grailoo; Bijan Alizadeh; Behjat Forouzandeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Hardware Trojans for Confidence Reduction and Misclassifications on Neural Networks. - Mahdieh Grailoo; Mairo Leier; Samuel Pagliarini (ISQED, 2022)

Preventing Distillation-based Attacks on Neural Network IP. - Mahdieh Grailoo; Zain Ul Abideen 002; Mairo Leier; Samuel Pagliarini (CoRR, 2022)

Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware Training. - Olle Hansson; Mahdieh Grailoo; Oscar Gustafsson; José L. Núñez-Yáñez (ARC, 2024)

Hardware Acceleration of Molecular Property Graph Prediction on a Heterogeneous Edge Platform. - Mahdieh Grailoo; Tooraj Nikoubin; José L. Núñez-Yáñez (NorCAS, 2024)

Leveraging Dynamic Range Analysis for Efficient Post-Training Quantization in Graph Convolutional Networks. - Hadi Mousanejad Jeddi; Mahdieh Grailoo; José L. Núñez-Yáñez (NorCAS, 2024)