Testing of high-speed DACs using PRBS generation with "Alternate-Bit-Tapping". - Mohit Singh; Mahendra Sakare; Shalabh Gupta (DATE, 2011)

A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology. - Mahendra Sakare; Mohit Singh; Shalabh Gupta (VDAT, 2012)

A high-speed PRBS generator using flip-flops employing feedback for distributed equalization. - Mahendra Sakare; Shalabh Gupta (ISCAS, 2014)

A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFE. - Pragya Maheshwari; Suhas Kaushik; Mahendra Sakare; Shalabh Gupta (VLSID, 2016)

A Quarter-Rate 27-1 Pseudo-Random Binary Sequence Generator Using Interleaved Architecture. - Mahendra Sakare (VLSID, 2016)

Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits. - Mahendra Sakare; Sadhu Pavan Kumar; Shalabh Gupta (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs. - Mahendra Sakare (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A low power 8 × 27-1 PRBS generator using Exclusive-OR gate merged D flip-flops. - Mayank Kumar Singh; Puneet Singh; Devarshi Mrinal Das; Mahendra Sakare (MWSCAS, 2021)

Design of a PRBS generator and a serializer using active inductor employed CML latch. - Puneet Singh; Mayank Kumar Singh; Vinayak Gopal Hande; Mahendra Sakare (MWSCAS, 2021)

Full CMOS Implementation of Bidirectional Associative Memory Neural Network with Analog Memristive Synapse. - Sahibia Kaur Vohra; Sherin A. Thomas; Mahendra Sakare; Devarshi Mrinal Das (MWSCAS, 2021)

Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing. - Sahibia Kaur Vohra; Sherin A. Thomas; Mahendra Sakare; Devarshi Mrinal Das (VDAT, 2021)

CMOS Circuit Implementation of Spiking Neural Network for Pattern Recognition Using On-chip Unsupervised STDP Learning. - Sahibia Kaur Vohra; Sherin A. Thomas; Mahendra Sakare; Devarshi Mrinal Das (CoRR, 2022)

A Double Cross-Coupled Delay Cell for High-Frequency Differential Ring VCOs. - Mayank Kumar Singh; Manish Kumar Gautam; Puneet Singh; Rajasekhar Nagulapalli; Devarshi Mrinal Das; Mahendra Sakare (APCCAS, 2023)

Analysing Mismatch effect of CMOS Neurons in Spiking Neural Network with Winner-take-all Mechanism. - Sahibia Kaur Vohra; Alex Pappachen James; Mahendra Sakare; Devarshi Mrinal Das (NorCAS, 2023)

A Low Power Differential Delay Cell without Cross-Coupled Latch for Ring VCO. - Mayank Kumar Singh; Puneet Singh; Devarshi Mrinal Das; Mahendra Sakare (PRIME, 2023)

Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse. - Sahibia Kaur Vohra; Sherin A. Thomas; Shivdeep; Mahendra Sakare; Devarshi Mrinal Das (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks. - Mayank Kumar Singh; Puneet Singh; Upendra Chichhula; Hirensh Mehra; Devarshi Mrinal Das; Mahendra Sakare (Circuits Syst. Signal Process., 2023)

A 5.4mW 12GHz Quadrature VCO using current reusing technique in 28nm CMOS technology. - Zahid Rashid Sheikh; Taranveer Kaur; Rajasekhar Nagulapalli; Hitesh Shrimali; Mahendra Sakare (ICCCNT, 2024)

Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons. - Sahibia Kaur Vohra; Sherin A. Thomas; Mahendra Sakare; Devarshi Mrinal Das (Integr., 2024)

A 2.9mW Inverter-based Quadrature Phase Clock Generator with ± 0.29° Phase Error. - Mayank Kumar Singh; M. Bhuvanesh; Rajasekhar Nagulapalli; Devarshi Mrinal Das; Mahendra Sakare (ISCAS, 2025)

SpiMAM: CMOS Implementation of Bio-Inspired Spiking Multidirectional Associative Memory Featuring In-Situ Learning. - Sahibia Kaur Vohra; Mahendra Sakare; Alex Pappachen James; Devarshi Mrinal Das (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)