One-Pass Redundancy Identification and Removal. - Miron Abramovici; Mahesh A. Iyer (ITC, 1992)

Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!"). - Mahesh A. Iyer; Miron Abramovici (ITC, 1994)

Low-Cost Redundancy Identification for Combinatorial Circuits. - Mahesh A. Iyer; Miron Abramovici (VLSI Design, 1994)

Identifying sequentially untestable faults using illegal states. - David E. Long; Mahesh A. Iyer; Miron Abramovici (VTS, 1995)

Energy models for delay testing. - Srimat T. Chakradhar; Mahesh A. Iyer; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Identifying Sequential Redundancies Without Search. - Mahesh A. Iyer; David E. Long; Miron Abramovici (DAC, 1996)

Surprises in Sequential Redundancy Identification. - Mahesh A. Iyer; David E. Long; Miron Abramovici (ED&TC, 1996)

FIRE: a fault-independent combinational redundancy identification algorithm. - Mahesh A. Iyer; Miron Abramovici (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Wavefront Technology Mapping. - Leon Stok; Andrew J. Sullivan; Mahesh A. Iyer (DATE, 1999)

A Robust Solution to the Timing Convergence Problem in High-Performance Design. - Narendra V. Shenoy; Mahesh A. Iyer; Robert F. Damiano; Kevin Harer; Hi-Keung Tony Ma; Paul Thilking (ICCD, 1999)

High Time For High Level ATPG. - Mahesh A. Iyer (ITC, 1999)

FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults. - David E. Long; Mahesh A. Iyer; Miron Abramovici (ACM Trans. Design Autom. Electr. Syst., 2000)

Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation. - Mahesh A. Iyer (ITC, 2003)

A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification. - Mahesh A. Iyer (MTV, 2003)

On improving optimization effectiveness in interconnect-driven physical synthesis. - Prashant Saxena; Vishal Khandelwal; Changge Qiao; Pei-Hsin Ho; J.-C. Lin; Mahesh A. Iyer (ISPD, 2009)

Detailed placement for modern FPGAs using 2D dynamic programming. - Shounak Dhar; Saurabh N. Adya; Love Singhal; Mahesh A. Iyer; David Z. Pan (ICCAD, 2016)

LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs. - Love Singhal; Mahesh A. Iyer; Saurabh N. Adya (DAC, 2017)

An Effective Timing-Driven Detailed Placement Algorithm for FPGAs. - Shounak Dhar; Mahesh A. Iyer; Saurabh N. Adya; Love Singhal; Nikolay Rubanov; David Z. Pan (ISPD, 2017)

CAD Opportunities with Hyper-Pipelining. - Mahesh A. Iyer (ISPD, 2017)

A shape-driven spreading algorithm using linear programming for global placement. - Shounak Dhar; Love Singhal; Mahesh A. Iyer; David Z. Pan (ASP-DAC, 2019)

FPGA Accelerated FPGA Placement. - Shounak Dhar; Love Singhal; Mahesh A. Iyer; David Z. Pan (FPL, 2019)

FPGA-Accelerated Spreading for Global Placement. - Shounak Dhar; Love Singhal; Mahesh A. Iyer; David Z. Pan (HPEC, 2019)

High-Definition Routing Congestion Prediction for Large-Scale FPGAs. - Mohamed Baker Alawieh; Wuxi Li; Yibo Lin; Love Singhal; Mahesh A. Iyer; David Z. Pan (ASP-DAC, 2020)

Symbiosis in Action: Reconfigurable Architectures and EDA. - Mahesh A. Iyer (FPGA, 2020)

Agilex™ Generation of Intel® FPGAs. - Ilya K. Ganusov; Mahesh A. Iyer; Ning Cheng; Alon Meisler (Hot Chips Symposium, 2020)

DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit. - Rachel Selina Rajarathnam; Mohamed Baker Alawieh; Zixuan Jiang; Mahesh A. Iyer; David Z. Pan (ASP-DAC, 2022)

DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs. - Rachel Selina Rajarathnam; Zixuan Jiang; Mahesh A. Iyer; David Z. Pan (ISPD, 2023)

A Software-Hardware Co-Optimized Toolkit for Deep Reinforcement Learning on Heterogeneous Platforms. - Yuan Meng 001; Michael Kinsner; Deshanand P. Singh; Mahesh A. Iyer; Viktor K. Prasanna (CoRR, 2023)

PEARL: Enabling Portable, Productive, and High-Performance Deep Reinforcement Learning using Heterogeneous Platforms. - Yuan Meng 001; Michael Kinsner; Deshanand P. Singh; Mahesh A. Iyer; Viktor K. Prasanna (CF, 2024)

Better Together: Combining Analytical and Annealing Methods for FPGA Placement. - Rachel Selina Rajarathnam; Kate Thurmer; Vaughn Betz; Mahesh A. Iyer; David Z. Pan (FPL, 2024)

A Heterogeneous Acceleration System for Attention-Based Multi-Agent Reinforcement Learning. - Samuel Wiggins; Yuan Meng 001; Mahesh A. Iyer; Viktor K. Prasanna (FPL, 2024)

A Partitioning-Based CAD Flow for Interposer-Based Multi-Die FPGAs. - Mahesh A. Iyer; Andrew B. Kahng; Jason Luu; Bodhisatta Pramanik; Kristofer Vorwerk; Grace Zgheib (FCCM, 2025)

Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. - Junius Pun; Xilai Dai; Grace Zgheib; Mahesh A. Iyer; Andrew Boutros; Vaughn Betz; Mohamed S. Abdelfattah (CoRR, 2025)

An Acceleration Framework for Deep Reinforcement Learning Using Heterogeneous Systems. - Yuan Meng 001; Mahesh A. Iyer; Viktor K. Prasanna (IEEE Trans. Parallel Distributed Syst., 2025)