FDT-a design tool for switched capacitor filters. - Sattam Dasgupta; Mahesh Mehendale; V. R. Sudershan; Rajeev Jain; Nagaraj Subramanyam; James Hochschild (ICCAD, 1989)

An approach to design flow management in CAD frameworks. - Mahesh Mehendale (EURO-DAC, 1991)

SLIM: A System for ASIC Library Management. - Mahesh Mehendale; P. Murugavel; M. Poornima (ICCAD, 1991)

A System for Behavior Extraction from FPGA Implementations of Synchronous Designs. - Mahesh Mehendale (VLSI Design, 1992)

MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs. - Mahesh Mehendale (DAC, 1993)

Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. - Mahesh Mehendale; Kaushik Roy 001 (VLSI Design, 1993)

Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures. - Mahesh Mehendale (VLSI Design, 1994)

An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis. - Mahesh Mehendale; Biswadip Mitra (VLSI Design, 1994)

Techniques for low power realization for FIR filters. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (ASP-DAC, 1995)

Synthesis of multiplier-less FIR filters with minimum number of additions. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (ICCAD, 1995)

AATMA: an algorithm for technology mapping for antifuse-based FPGAs. - Mahesh Mehendale; M. K. Ram Prasad (VLSI Design, 1995)

Optimized Code Generation of Multiplication-free Linear Transforms. - Mahesh Mehendale; G. Venkatesh 001; Sunil D. Sherlekar (DAC, 1996)

Low power realization of FIR filters using multirate architectures. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (VLSI Design, 1996)

Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (VLSI Design, 1997)

Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. - Mahesh Mehendale; Amit Sinha; Sunil D. Sherlekar (ASP-DAC, 1998)

Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. - Mahesh Mehendale; Somdipta Basu Roy; Sunil D. Sherlekar; G. Venkatesh 001 (VLSI Design, 1998)

Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (VLSI Design, 1998)

Extensions to Programmable DSP architectures for Reduced Power Dissipation. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (VLSI Design, 1998)

mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic. - Amit Sinha; Mahesh Mehendale (VLSI Design, 1998)

Low-power realization of FIR filters on programmable DSPs. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Integrated IC design approach based on software engineering paradigm. - Sunsil Sinha; Mahesh Mehendale (CICC, 1999)

Improving performance of high precision signal processing algorithms on programmable DSPs. - M. N. Mahesh; Mahesh Mehendale (ISCAS (3), 1999)

Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms. - M. N. Mahesh; Satrajit Gupta; Mahesh Mehendale (VLSI Design, 1999)

Low Power Code Generation of Multiplication-free Linear Transforms. - Mahesh Mehendale; Sunil D. Sherlekar (VLSI Design, 1999)

Low Power Realization of Residue Number System Based FIR Filters. - M. N. Mahesh; Mahesh Mehendale (VLSI Design, 2000)

Power Reduction Techniques for Portable DSP Applications. - Mahesh Mehendale; Sunil D. Sherlekar (VLSI Design, 2000)

High Level Synthesis Of Multi-Precision Data Flow Graphs. - Vikas Agrawal; Anand Pande; Mahesh Mehendale (VLSI Design, 2001)

Performance Considerations in Embedded DSP based System-On-a-Chip Designs. - Ajit Gupte; Mahesh Mehendale; Ramesh Ramamritham; Deepa Nair (VLSI Design, 2001)

Functional Verification of Programmable DSP Cores. - Mahesh Mehendale; Santhosh Kumar Amanna (VLSI Design, 2001)

Emerging markets: design goes global. - Chi-Foon Chan; Deirdre Hanford; Jian Yue Pan; Narendra V. Shenoy; Mahesh Mehendale; A. Vasudevan; Shaojun Wei (DAC, 2003)

Multivoltage scheduling with voltage-partitioned variable storage. - Amitabh Menon; S. K. Nandy 001; Mahesh Mehendale (ISLPED, 2003)

Challenges in the Design of Embedded Real-time DSP SoCs. - Mahesh Mehendale (VLSI Design, 2004)

SoC - The Road Ahead. - Mahesh Mehendale (VLSI Design, 2006)

Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. - Subash Chandar G.; Mahesh Mehendale; R. Govindarajan (J. VLSI Signal Process., 2006)

Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs. - Nagendra Dwarakanath Gulur; R. Manikantan; R. Govindarajan; Mahesh Mehendale (PACT, 2011)

Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding. - Ajit Gupte; Bharadwaj Amrutur; Mahesh Mehendale; Ajit V. Rao; Madhukar Budagavi (IEEE Trans. Circuits Syst. Video Technol., 2011)

Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. - Nagendra Dwarakanath Gulur; R. Manikantan; Mahesh Mehendale; R. Govindarajan (ICS, 2012)

A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC. - Mahesh Mehendale; Subrangshu Das; Mohit Sharma; Mihir N. Mody; Ratna Reddy; Joseph P. Meehan; Hideo Tamama; Brian Carlson; Mike Polley (ISSCC, 2012)

A monolithic programmable Ultra-HD video codec engine. - Hetul Sanghvi; Mihir N. Mody; Niraj Nandan; Mahesh Mehendale; Subrangshu Das; Dipan Kumar Mandal; Nainala Vyagrheswarudu; Vijayavardhan Baireddy; Pavan Shastry (ICASSP, 2014)

A 28nm programmable and low power ultra-HD video codec engine. - Hetul Sanghvi; Mihir N. Mody; Niraj Nandan; Mahesh Mehendale; Subrangshu Das; Dipan Kumar Mandal; Pavan Shastry (ISCAS, 2014)

Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. - Nagendra Dwarakanath Gulur; Mahesh Mehendale; R. Manikantan; R. Govindarajan (MICRO, 2014)

ANATOMY: an analytical model of memory system performance. - Nagendra Gulur; Mahesh Mehendale; Raman Manikantan; Ramaswamy Govindarajan (SIGMETRICS, 2014)

Accelerating H.264/HEVC video slice processing using application specific instruction set processor. - Dipan Kumar Mandal; Mihir Mody; Mahesh Mehendale; Naresh Yadav; Ghone Chaitanya; Piyali Goswami; Hetul Sanghvi; Niraj Nandan (ICCE, 2015)

8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process. - Vipul Kumar Singhal 001; Vinod Menezes; Srinivasa Chakravarthy; Mahesh Mehendale (ISSCC, 2015)

A Comprehensive Analytical Performance Model of DRAM Caches. - Nagendra Dwarakanath Gulur; Mahesh Mehendale; Ramaswamy Govindarajan (ICPE, 2015)

F1: Designing secure systems: Manufacturing, circuits and architectures. - Vivek De; Kerry Bernstein; Takefumi Yoshikawa; Yusuf Leblebici; Marian Verhelst; Mahesh Mehendale; Makoto Nagata (ISSCC, 2016)

Session 4 overview: Digital processors. - Mahesh Mehendale; Luke Shin (ISSCC, 2016)

MicroRefresh: Minimizing Refresh Overhead in DRAM Caches. - Nagendra Gulur; R. Govindarajan; Mahesh Mehendale (MEMSYS, 2016)

Session 14 overview: Deep-learning processors. - Takashi Hashimoto; Mahesh Mehendale; Byeong-Gyu Nam (ISSCC, 2017)

A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. - R. R. Manikandan; Vipul Kumar Singhal 001; Rajat Chauhan; Vinod Menezes; Mahesh Mehendale (VLSID, 2018)

DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. - Hassan Dbouk; Hetul Sanghvi; Mahesh Mehendale; Naresh R. Shanbhag (ECCV (27), 2020)

150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications. - Vipul Singhal 001; Rajat Chauhan; Vinod Menezes; R. R. Manikandan; Raveesh Magod; Mahesh Mehendale; Anantha P. Chandrakasan (VLSID, 2021)

An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications. - Avishek Biswas; Hetul Sanghvi; Mahesh Mehendale; G. Preet (CICC, 2022)

Live Demonstration: Audio Inference using Neuromorphic Cochlea on RAMAN Accelerator. - Adithya Krishna; Hitesh Pavan Oleti; Anand Chauhan; H. Shankaranarayanan; André van Schaik; Mahesh Mehendale; Chetan Singh Thakur (BioCAS, 2023)

A Sparsity-driven tinyML Accelerator for Decoding Hand Kinematics in Brain-Computer Interfaces. - Adithya Krishna; Vignesh Ramanathan; Satyapreet Singh Yadav; Sahil Shah; André van Schaik; Mahesh Mehendale; Chetan Singh Thakur (BioCAS, 2023)

RAMAN: A Re-configurable and Sparse tinyML Accelerator for Inference on Edge. - Adithya Krishna; Srikanth Rohit Nudurupati; Chandana D. G; Pritesh Dwivedi; André van Schaik; Mahesh Mehendale; Chetan Singh Thakur (CoRR, 2023)

Live Demonstration: Real-time audio and visual inference on the RAMAN TinyML accelerator. - Adithya Krishna; Ashwin Rajesh; Hitesh Pavan Oleti; Anand Chauhan; Shankaranarayanan H; André van Schaik; Mahesh Mehendale; Chetan Singh Thakur (ISCAS, 2024)

RAMAN: A Reconfigurable and Sparse tinyML Accelerator for Inference on Edge. - Adithya Krishna; Srikanth Rohit Nudurupati; Chandana D. G; Pritesh Dwivedi; André van Schaik; Mahesh Mehendale; Chetan Singh Thakur (IEEE Internet Things J., 2024)

Neural Signal Compression using RAMAN tinyML Accelerator for BCI Applications. - Adithya Krishna; Sohan Debnath; André van Schaik; Mahesh Mehendale; Chetan Singh Thakur (CoRR, 2025)

HOMI: Ultra-Fast EdgeAI platform for Event Cameras. - Shankaranarayanan H; Satyapreet Singh Yadav; Adithya Krishna; Ajay Vikram P; Mahesh Mehendale; Chetan Singh Thakur (CoRR, 2025)