A Disturb Free Read Port 8T SRAM Bitcell Circuit Design with Virtual Ground Scheme. - Mahmood Uddin Mohammed; Nahid M. Hossain; Masud H. Chowdhury (MWSCAS, 2018)

Novel CNTFET and Memristor based Unbalanced Ternary Logic Gate. - Mahmood Uddin Mohammed; Rakesh Vijjapuram; Masud H. Chowdhury (MWSCAS, 2018)

Reliability and Energy Efficiency of the Tunneling Transistor-Based 6T SRAM Cell in Sub-10 nm Domain. - Mahmood Uddin Mohammed; Masud H. Chowdhury (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Design of Energy Efficient SRAM Cell Based on Double Gate Schottky-Barrier-Type GNRFET with Minimum Dimer Lines. - Mahmood Uddin Mohammed; Masud H. Chowdhury (ISCAS, 2019)

A Low Leakage SRAM Bitcell Design Based on MOS-Type Graphene Nano-Ribbon FET. - Mahmood Uddin Mohammed; Athiya Nizam; Liaquat Ali; Masud H. Chowdhury (ISCAS, 2019)

FinFET based SRAMs in Sub-10nm domain. - Mahmood Uddin Mohammed; Athiya Nizam; Liaquat Ali; Masud H. Chowdhury (Microelectron. J., 2021)