SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture. - Ahmed S. Eissa; Mahmoud A. Elmohr; Mostafa A. Saleh; Khaled E. Ahmed; Mohammed M. Farag (ASAP, 2016)

Hardware implementation of a SHA-3 application-specific instruction set processor. - Mahmoud A. Elmohr; Mostafa A. Saleh; Ahmed S. Eissa; Khaled E. Ahmed; Mohammed M. Farag (ICM, 2016)

A reusable verification environment for NoC platforms using UVM. - Ahmed S. Eissa; Moamen A. Ibrahem; Mahmoud A. Elmohr; Yasmin Zamzam; Ahmed El-Yamany; Sameh El-Ashry; Mostafa Khamis; Ahmed Shalaby 001 (EUROCON, 2017)

A Hardware-Efficient Implementation of CLOC for On-chip Authenticated Encryption. - Mahmoud A. Elmohr; Sachin Kumar; Mustafa Khairallah; Anupam Chattopadhyay (ISVLSI, 2018)

RVNoC: A Framework for Generating RISC-V NoC-Based MPSoC. - Mahmoud A. Elmohr; Ahmed S. Eissa; Moamen Ibrahim; Mostafa Khamis; Sameh El-Ashry; Ahmed Shalaby 001; Mohamed Abdelsalam; M. Watheq El-Kharashi (PDP, 2018)

Going Deep: Using deep learning techniques with simplified mathematical models against XOR BR and TBR PUFs (Attacks and Countermeasures). - Mahmoud Khalafalla; Mahmoud A. Elmohr; Catherine H. Gebotys (HOST, 2020)

EM Fault Injection on ARM and RISC-V. - Mahmoud A. Elmohr; Haohao Liao; Catherine H. Gebotys (ISQED, 2020)

TurboHE: Accelerating Fully Homomorphic Encryption Using FPGA Clusters. - Haohao Liao; Mahmoud A. Elmohr; Xuan Dong; Yanjun Qian; Wenzhe Yang 002; Zhiwei Shang; Yin Tan (IPDPS, 2023)