Low power SOVA architecture using bi-directional scheme. - Mahmoud Elassal; Magdy A. Bayoumi (ISCAS (1), 2002)

Power efficient architecture for (3, 6)-regular low-density parity-check code decoder. - Yijun Li; Mahmoud Elassal; Magdy A. Bayoumi (ISCAS (4), 2004)

A systematic framework for high throughput MAP decoder VLSI architectures. - Mahmoud Elassal; Ashok Kumar 001; Magdy A. Bayoumi (ISCAS (1), 2005)