Design of a two-capacitor sample & hold circuit using a two-stage OTA with hybrid cascode compensation. - Mahmoud Zangeneh; Hossein Aghababa; Behjat Forouzandeh (ECCTD, 2009)

An analytical delay reduction strategy for buffer-inserted global interconnects in VDSM technologies. - Mahmoud Zangeneh; Nasser Masoumi (ECCTD, 2009)

Statistical delay modeling of read operation of SRAMs due to channel length variation. - Hossein Aghababa; Mahmoud Zangeneh; Ali Afzali-Kusha; Behjat Forouzandeh (ISCAS, 2010)

Performance and energy models for memristor-based 1T1R RRAM cell. - Mahmoud Zangeneh; Ajay Joshi (ACM Great Lakes Symposium on VLSI, 2012)

Sub-threshold logic circuit design using feedback equalization. - Mahmoud Zangeneh; Ajay Joshi (DATE, 2014)

Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM. - Mahmoud Zangeneh; Ajay Joshi (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Detecting hardware trojans using backside optical imaging of embedded watermarks. - Boyou Zhou; Ronen Adato; Mahmoud Zangeneh; Tianyu Yang; Aydan Uyar; Bennett B. Goldberg; M. Selim Ünlü; Ajay Joshi (DAC, 2015)

Dictionary-based sparse representation for resolution improvement in laser voltage imaging of CMOS integrated circuits. - T. Berkin Cilingiroglu; Mahmoud Zangeneh; Aydan Uyar; W. Clem Karl; Janusz Konrad; Ajay Joshi; Bennett B. Goldberg; M. Selim Ünlü (DATE, 2015)

Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization. - Mahmoud Zangeneh; Ajay Joshi (IEEE Trans. Very Large Scale Integr. Syst., 2016)