Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier. - Mahmut Yilmaz; Derek Hower; Sule Ozev; Daniel J. Sorin (ITC, 2006)

Applying architectural vulnerability Analysis to hard faults in the microprocessor. - Fred A. Bower; Derek Hower; Mahmut Yilmaz; Daniel J. Sorin; Sule Ozev (SIGMETRICS/Performance, 2006)

Lazy Error Detection for Microprocessor Functional Units. - Mahmut Yilmaz; Albert Meixner; Sule Ozev; Daniel J. Sorin (DFT, 2007)

Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. - Sule Ozev; Daniel J. Sorin; Mahmut Yilmaz (ICCD, 2007)

Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects. - Mahmut Yilmaz; Krishnendu Chakrabarty; Mohammad Tehranipoor (ITC, 2008)

Test-Pattern Grading and Pattern Selection for Small-Delay Defects. - Mahmut Yilmaz; Krishnendu Chakrabarty; Mohammad Tehranipoor (VTS, 2008)

Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects. - Mahmut Yilmaz; Krishnendu Chakrabarty (DATE, 2009)

Automated Test Grading and Pattern Selection for Small-Delay Defects. - Mahmut Yilmaz (2009)

Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. - Sandeep Kumar Goel; Krishnendu Chakrabarty; Mahmut Yilmaz; Ke Peng; Mohammad Tehranipoor (Asian Test Symposium, 2010)

A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection. - Ke Peng; Mahmut Yilmaz; Krishnendu Chakrabarty; Mohammad Tehranipoor (Asian Test Symposium, 2010)

High-quality pattern selection for screening small-delay defects considering process variations and crosstalk. - Ke Peng; Mahmut Yilmaz; Mohammad Tehranipoor; Krishnendu Chakrabarty (DATE, 2010)

RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage. - Alodeep Sanyal; Krishnendu Chakrabarty; Mahmut Yilmaz; Hideo Fujiwara (ITC, 2010)

The scan-DFT features of AMD's next-generation microprocessor core. - Mahmut Yilmaz; Baosheng Wang; Jayalakshmi Rajaraman; Tom Olsen; Kanwaldeep Sobti; Dwight Elvey; Jeff Fitzgerald; Grady Giles; Wei-Yu Chen (ITC, 2010)

A novel hybrid method for SDD pattern grading and selection. - Ke Peng; Jason Thibodeau; Mahmut Yilmaz; Krishnendu Chakrabarty; Mohammad Tehranipoor (VTS, 2010)

Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits. - Mahmut Yilmaz; Krishnendu Chakrabarty; Mohammad Tehranipoor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Critical Fault-Based Pattern Generation for Screening SDDs. - Fang Bao; Ke Peng; Mahmut Yilmaz; Krishnendu Chakrabarty; LeRoy Winemberg; Mohammad Tehranipoor (ETS, 2011)

A Metric to Target Small-Delay Defects in Industrial Circuits. - Mahmut Yilmaz; Mohammad Tehranipoor; Krishnendu Chakrabarty (IEEE Des. Test Comput., 2011)

Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization. - Stephan Eggersglüß; Mahmut Yilmaz; Krishnendu Chakrabarty (Asian Test Symposium, 2012)

Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults. - Fang Bao; Ke Peng; Mahmut Yilmaz; Krishnendu Chakrabarty; LeRoy Winemberg; Mohammad Tehranipoor (J. Electron. Test., 2013)

Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects. - Ke Peng; Mahmut Yilmaz; Krishnendu Chakrabarty; Mohammad Tehranipoor (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Circuit Path Grading Considering Layout, Process Variations, and Cross Talk. - Ke Peng; Mahmut Yilmaz; Mohammad Tehranipoor (Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2014)

Output Deviations-Based SDD Testing. - Mahmut Yilmaz (Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2014)

Advanced test methodology for complex SoCs. - Pavan Kumar Datla Jagannadha; Mahmut Yilmaz; Milind Sonawane; Sailendra Chadalavada; Shantanu Sarangi; Bonita Bhaskaran; Ayub Abdollahian (ITC, 2016)

Flexible scan interface architecture for complex SoCs. - Milind Sonawane; Sailendra Chadalavada; Shantanu Sarangi; Amit Sanghani; Mahmut Yilmaz; Pavan Kumar Datla Jagannadha; Jonathon E. Colburn (VTS, 2016)

Dynamic docking architecture for concurrent testing and peak power reduction. - Milind Sonawane; Pavan Kumar Datla Jagannadha; Sailendra Chadalavada; Shantanu Sarangi; Mahmut Yilmaz; Amit Sanghani; Karthikeyan Natarajan; Jonathon E. Colburn; Anubhav Sinha (VTS, 2016)

Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms. - Pavan Kumar Datla Jagannadha; Mahmut Yilmaz; Milind Sonawane; Sailendra Chadalavada; Shantanu Sarangi; Bonita Bhaskaran; Shashank Bajpai; Venkat Abilash Reddy Nerallapally; Jayesh Pandey; Sam Jiang (VTS, 2019)

On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST). - Seyed Nima Mozaffari; Bonita Bhaskaran; Shantanu Sarangi; Suhas M. Satheesh; Kuo Lin Fu; Nithin Valentine; P. Manikandan; Mahmut Yilmaz (VTS, 2022)

NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links. - Mahmut Yilmaz; Pavan Kumar Datla Jagannadha; Kaushik Narayanun; Shantanu Sarangi; Francisco Da Silva; Joe Sarmiento; Smbat Tonoyan; Ashwin Chintaluri; Animesh Khare; Milind Sonawane; Ashish Kumar; Anitha Kalva; et al. (VTS, 2022)

NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links. - Mahmut Yilmaz; Pavan Kumar Datla Jagannadha; Kaushik Narayanun; Shantanu Sarangi; Francisco Da Silva; Joe Sarmiento (IEEE Des. Test, 2023)

A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS. - Kunal Jain Mangilal; Mahmut Yilmaz; Vishal Agarwal; Shantanu Sarangi; Kaushik Narayanun (ITC, 2024)