A Novel Scan Architecture for Low Power Scan-Based Testing. - Mahshid Mojtabavi Naeini; Chia Yee Ooi (VLSI Design, 2015)

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell. - Mahshid Mojtabavi Naeini; Sreedharan Baskara Dass; Chia Yee Ooi; Tomokazu Yoneda; Michiko Inoue (Integr., 2017)