Advanced Dataflow Programming using Actor Machines for High-Level Synthesis. - Endri Bezati; Mahyar Emami; James R. Larus (FPGA, 2020)

Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems. - Mahyar Emami; Endri Bezati; Jörn W. Janneck; James R. Larus (FPGA, 2021)

StreamBlocks: A compiler for heterogeneous dataflow computing (technical report). - Endri Bezati; Mahyar Emami; Jörn W. Janneck; James R. Larus (CoRR, 2021)

Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks. - Mahyar Emami; Endri Bezati; Jörn W. Janneck; James R. Larus (PACT, 2022)

Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats. - Sahand Kashani; Mahyar Emami; James R. Larus (FPL, 2022)

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism. - Mahyar Emami; Sahand Kashani; Keisuke Kamahori; Mohammad Sepehr Pourghannad; Ritik Raj; James R. Larus (ASPLOS (4), 2023)

A 475 MHz Manycore FPGA Accelerator for RTL Simulation. - Sahand Kashani; Mahyar Emami; Keisuke Kamahori; Mohammad Sepehr Pourghannad; Ritik Raj; James R. Larus (FPGA, 2024)

Performance Interfaces for Hardware Accelerators. - Jiacheng Ma 002; Rishabh R. Iyer; Sahand Kashani; Mahyar Emami; Thomas Bourgeat; George Candea (OSDI, 2024)

Parendi: Thousand-Way Parallel RTL Simulation. - Mahyar Emami; Thomas Bourgeat; James R. Larus (ASPLOS (2), 2025)