A Simple Central Processing Unit with Multi-Dimensional Logarithmic Number System Extensions. - Mahzad Azarmehr; Roberto Muscedere (ASAP, 2007)

Recursive architectures for 2DLNS multiplication. - Mahzad Azarmehr; Majid Ahmadi; Graham A. Jullien (ISCAS, 2010)

High-speed CMOS track-and-hold with an offset cancellation replica circuit. - Mahzad Azarmehr; Rashid Rashidzadeh; Majid Ahmadi (ISCAS, 2010)

High-speed and low-power reconfigurable architectures of 2-digit two-dimensional logarithmic number system-based recursive multipliers. - Mahzad Azarmehr; Mohammad M. Ahmadi; Graham A. Jullien; Roberto Muscedere (IET Circuits Devices Syst., 2010)

A RISC architecture for 2DLNS-based signal processing. - Mahzad Azarmehr; Roberto Muscedere (Int. J. High Perform. Syst. Archit., 2011)

Arithmetic with the Two-Dimensional Logarithmic Number System (2DLNS). - Mahzad Azarmehr (2011)

Low-Power Finite Impulse Response (FIR) Filter Design Using Two-Dimensional Logarithmic Number System (2DLNS) Representations. - Mahzad Azarmehr; Majid Ahmadi (Circuits Syst. Signal Process., 2012)

Low-power oscillator for passive radio frequency identification transponders. - Mahzad Azarmehr; Rashid Rashidzadeh; Majid Ahmadi (IET Circuits Devices Syst., 2012)

Wireless device identification using oscillator control voltage as RF fingerprint. - Mahzad Azarmehr; Ankit Mehta; Rashid Rashidzadeh (CCECE, 2017)

Secure authentication and access mechanism for IoT wireless sensors. - Mahzad Azarmehr; Arash Ahmadi; Rashid Rashidzadeh (ISCAS, 2017)