A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS. - Masanori Furuta; Mai Nozawa; Tetsuro Itakura (ISSCC, 2010)

A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique. - Masanori Furuta; Mai Nozawa; Tetsuro Itakura (IEEE J. Solid State Circuits, 2011)

A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. - Takashi Toi; Junji Wadatsumi; Hiroyuki Kobayashi; Yutaka Shimizu; Yuji Satoh; Makoto Morimoto; Rui Ito; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Go Urakawa; Jun Deguchi (ISSCC, 2019)

A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR. - Fumihiko Tachibana; Huy Cu Ngo; Go Urakawa; Takashi Toi; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Junji Wadatsumi; Hiroyuki Kobayashi; Jun Deguchi (ESSCIRC, 2022)

A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. - Takashi Toi; Junji Wadatsumi; Hiroyuki Kobayashi; Yutaka Shimizu; Yuji Satoh; Makoto Morimoto; Rui Ito; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Go Urakawa; Jun Deguchi; et al. (IEEE J. Solid State Circuits, 2022)

A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver. - Fumihiko Tachibana; Huy Cu Ngo; Go Urakawa; Takashi Toi; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Junji Wadatsumi; Hiroyuki Kobayashi; Jun Deguchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)