Enhanced Reusability for SoC-Based HW/SW Co-Design. - Maik Boden; Jörg Schneider; Klaus Feske; Steffen Rülke (DSD, 2002)

Eine wiederverwendungsgerechte Entwurfsmethodik für rekonfigurierbare SoC-Architekturen. - Jörg Schneider; Maik Boden; Steffen Rülke (MBMV, 2002)

Cost-Efficient Implementation of Adaptive Finite State Machines. - Maik Boden; Manfred Koegst; José Luis Tiburcio Badía; Steffen Rülke (DSD, 2004)

A Low-Cost Realization of an Adaptable Protocol Processing Unit. - Maik Boden; Alex Gleich; Steffen Rülke; Ulrich Nageldinger (IPDPS, 2005)

A high-level target-precise model for designing reconfigurable HW tasks. - Maik Boden; Steffen Rülke; Jürgen Becker 001 (IPDPS, 2006)

High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs. - Maik Boden; Thomas Fiebig; Torsten Meibner; Steffen Rülke; Jürgen Becker 001 (IPDPS, 2007)

GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs. - Maik Boden; Thomas Fiebig; Markus Reiband; Peter Reichel; Steffen Rülke (ISVLSI, 2008)