High Performance Single-Chip FPGA Rijndael Algorithm Implementations. - Máire McLoone; John V. McCanny (CHES, 2001)

Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm. - Máire McLoone; John V. McCanny (FPL, 2001)

Efficient single-chip implementation of SHA-384 and SHA-512. - Máire McLoone; John V. McCanny (FPT, 2002)

Generic silicon architectures for encryption algorithm. - Máire McLoone (2002)

Very High Speed 17 Gbps SHACAL Encryption Architecture. - Máire McLoone; John V. McCanny (FPL, 2003)

A high-speed, low latency RSA decryption silicon core. - Ciaran McIvor; Máire McLoone; John V. McCanny (ISCAS (4), 2003)

Rijndael FPGA Implementations Utilising Look-Up Tables. - Máire McLoone; John V. McCanny (J. VLSI Signal Process., 2003)

FPGA Montgomery Multiplier Architectures - A Comparison. - Ciaran McIvor; Máire McLoone; John V. McCanny (FCCM, 2004)

Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication. - Máire McLoone; Ciaran McIvor; John V. McCanny (FPT, 2004)

FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). - Ciaran McIvor; Máire McLoone; John V. McCanny (ISCAS (3), 2004)

Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor. - P. Moore; Máire McLoone; Sakir Sezer (AICT/SAPIR/ELETE, 2005)

High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. - Ciaran McIvor; Máire McLoone; John V. McCanny (FPT, 2005)

High-Speed Hardware Architectures of the Whirlpool Hash Function. - Máire McLoone; Ciaran McIvor; Aidan Savage (FPT, 2005)

An Adaptable And Scalable Asymmetric Cryptographic Processor. - Neil Smyth; Máire McLoone; John V. McCanny (ASAP, 2006)

Limitations of existing wireless networks authentication and key management techniques for MANETs. - Ghazanfar Ali Safdar; Clare McGrath; Máire McLoone (ISCN, 2006)

Hardware Elliptic Curve Cryptographic Processor Over $ rm GF(p)$. - Ciaran McIvor; Máire McLoone; John V. McCanny (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

WLAN security processor. - Neil Smyth; Máire McLoone; John V. McCanny (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Public Key Cryptography and RFID Tags. - Máire McLoone; Matthew J. B. Robshaw (CT-RSA, 2007)

Exploring technology related design-space limitations of high performance network processing. - John V. McCanny; Sakir Sezer; Máire O'Neill (ESSCIRC, 2007)

New Architectures for Low-Cost Public Key Cryptography on RFID Tags. - Máire McLoone; Matthew J. B. Robshaw (ISCAS, 2007)

Identity Based Public Key Exchange (IDPKE) for Wireless Ad Hoc Networks. - Clare McGrath; Ghazanfar Ali Safdar; Máire McLoone (SECRYPT, 2007)

MONET Special Issue on Next Generation Hardware Architectures for Secure Mobile Computing. - Nicolas Sklavos 001; Máire McLoone; Xinmiao Zhang 001 (Mob. Networks Appl., 2007)

High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function. - Máire McLoone; Ciaran McIvor (J. VLSI Signal Process., 2007)

FPGA implementation and analysis of random delay insertion countermeasure against DPA. - Yingxi Lu; Máire O'Neill; John V. McCanny (FPT, 2008)

Differential Power Analysis of a SHACAL-2 hardware implementation. - Yingxi Lu; Máire O'Neill; John V. McCanny (ISCAS, 2008)

Is the differential frequency-based attack effective against random delay insertion? - Yingxi Lu; Keanhong Boey; Máire O'Neill; John V. McCanny; Akashi Satoh (SiPS, 2009)

ASIC evaluation of ECHO hash function. - Liang Lu; Máire O'Neill; Earl E. Swartzlander Jr. (SoCC, 2009)

Common Control Channel Security Framework for Cognitive Radio Networks. - Ghazanfar Ali Safdar; Máire O'Neill (VTC Spring, 2009)

Performance Analysis of Novel Randomly Shifted Certification Authority Authentication Protocol for MANETs. - Ghazanfar Ali Safdar; Máire O'Neill (EURASIP J. Wirel. Commun. Netw., 2009)

Random clock against differential power analysis. - Keanhong Boey; Yingxi Lu; Máire O'Neill; Roger F. Woods (APCCAS, 2010)

SEED masking implementations against power analysis attacks. - Yingxi Lu; Keanhong Boey; Philip Hodgers; Máire O'Neill (APCCAS, 2010)

FPGA Implementations of the Round Two SHA-3 Candidates. - Brian Baldwin; Andrew Byrne; Liang Lu; Mark Hamilton; Neil Hanley; Máire O'Neill; William P. Marnane (FPL, 2010)

Lightweight DPA resistant solution on FPGA to counteract power models. - Yingxi Lu; Keanhong Boey; Philip Hodgers; Máire O'Neill (FPT, 2010)

Security of AES Sbox designs to power analysis. - Keanhong Boey; Philip Hodgers; Yingxi Lu; Máire O'Neill; Roger F. Woods (ICECS, 2010)

Differential Power Analysis of CAST-128. - Keanhong Boey; Yingxi Lu; Máire O'Neill; Roger F. Woods (ISVLSI, 2010)

QCA Systolic Matrix Multiplier. - Liang Lu; Weiqiang Liu 001; Máire O'Neill; Earl E. Swartzlander Jr. (ISVLSI, 2010)

A Hardware Wrapper for the SHA-3 Hash Algorithms. - Brian Baldwin; Andrew Byrne; Liang Lu; Mark Hamilton; Neil Hanley; Máire O'Neill; William P. Marnane (IACR Cryptol. ePrint Arch., 2010)

On Foundation and Construction of Physical Unclonable Functions. - Jiang Wu; Máire O'Neill (IACR Cryptol. ePrint Arch., 2010)

Low-cost digital signature architecture suitable for radio frequency identification tags. - Máire O'Neill; Matthew J. B. Robshaw (IET Comput. Digit. Tech., 2010)

Evaluation of Random Delay Insertion against DPA on FPGAs. - Yingxi Lu; Máire O'Neill; John V. McCanny (ACM Trans. Reconfigurable Technol. Syst., 2010)

Power Spectral Density Side Channel Attack Overlapping Window Method. - Philip Hodgers; Keanhong Boey; Máire O'Neill (DSD, 2011)

Design rules for Quantum-dot Cellular Automata. - Weiqiang Liu 001; Liang Lu; Máire O'Neill; Earl E. Swartzlander Jr. (ISCAS, 2011)

How Resistant are Sboxes to Power Analysis Attacks? - Keanhong Boey; Máire O'Neill; Roger F. Woods (NTMS, 2011)

A Forward Private Protocol based on PRNG and LPN for Low-cost RFID . - Xiaolin Cao; Máire O'Neill (SECRYPT, 2011)

A Private and Scalable Authentication for RFID Systems Using Reasonable Storage. - Xiaolin Cao; Máire O'Neill (TrustCom, 2011)

Variable window power spectral density attack. - Philip Hodgers; Keanhong Boey; Máire O'Neill (WIFS, 2011)

A review of QCA adders and metrics. - Weiqiang Liu 001; Máire O'Neill; Earl E. Swartzlander Jr. (ACSCC, 2012)

The improved sign bit encryption of motion vectors for H.264/AVC. - Yongsheng Wang; Máire O'Neill; Fatih Kurugollu (EUSIPCO, 2012)

Application-oriented SHA-256 hardware design for low-cost RFID. - Xiaolin Cao; Máire O'Neill (ISCAS, 2012)

Cost-efficient decimal adder design in Quantum-dot cellular automata. - Weiqiang Liu 001; Liang Lu; Máire O'Neill; Earl E. Swartzlander Jr. (ISCAS, 2012)

Adaptive binary mask for privacy region protection. - Yongsheng Wang; Máire O'Neill; Fatih Kurugollu (ISCAS, 2012)

Hardware Comparison of the ISO/IEC 29192-2 Block Ciphers. - Neil Hanley; Máire O'Neill (ISVLSI, 2012)

Self-Timed Physically Unclonable Functions. - Julian P. Murphy; Máire O'Neill; Frank P. Burns; Alexandre V. Bystrov; Alexandre Yakovlev; Basel Halak (NTMS, 2012)

A novel common control channel security framework for cognitive radio networks. - Ghazanfar Ali Safdar; Máire O'Neill (Int. J. Auton. Adapt. Commun. Syst., 2012)

A tunable selective encryption scheme for H.264/AVC. - Yongsheng Wang; Máire O'Neill; Fatih Kurugollu (EUVIP, 2013)

Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE. - Ciara Moore; Neil Hanley; John McAllister; Máire O'Neill; Elizabeth O'Sullivan; Xiaolin Cao (Financial Cryptography Workshops, 2013)

Pre-processing power traces with a phase-sensitive detector. - Philip Hodgers; Neil Hanley; Máire O'Neill (HOST, 2013)

Privacy region protection for H.264/AVC by encrypting the intra prediction modes without drift error in I frames. - Yongsheng Wang; Máire O'Neill; Fatih Kurugollu (ICASSP, 2013)

Power analysis attack of QCA circuits: A case study of the Serpent cipher. - Weiqiang Liu 001; Saket Srivastava; Liang Lu; Máire O'Neill; Earl E. Swartzlander Jr. (ISCAS, 2013)

Partial encryption by randomized zig-zag scanning for video encoding. - Yongsheng Wang; Máire O'Neill; Fatih Kurugollu (ISCAS, 2013)

Accelerating Fully Homomorphic Encryption over the Integers with Super-size Hardware Multiplier and Modular Reduction. - Xiaolin Cao; Ciara Moore; Máire O'Neill; Elizabeth O'Sullivan; Neil Hanley (IACR Cryptol. ePrint Arch., 2013)

QCA Systolic Array Design. - Liang Lu; Weiqiang Liu 001; Máire O'Neill; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 2013)

A Tunable Encryption Scheme and Analysis of Fast Selective Encryption for CAVLC and CABAC in H.264/AVC. - Yongsheng Wang; Máire O'Neill; Fatih Kurugollu (IEEE Trans. Circuits Syst. Video Technol., 2013)

New FMO type to flag ROI in H.264/AVC. - Yongsheng Wang; Máire O'Neill; Fatih Kurugollu (EUVIP, 2014)

High-Speed Fully Homomorphic Encryption Over the Integers. - Xiaolin Cao; Ciara Moore; Máire O'Neill; Neil Hanley; Elizabeth O'Sullivan (Financial Cryptography Workshops, 2014)

A unique and robust single slice FPGA identification generator. - Chongyan Gu; Julian P. Murphy; Máire O'Neill (ISCAS, 2014)

Practical homomorphic encryption: A survey. - Ciara Moore; Máire O'Neill; Elizabeth O'Sullivan; Yarkin Doröz; Berk Sunar (ISCAS, 2014)

Empirical evaluation of multi-device profiling side-channel attacks. - Neil Hanley; Máire O'Neill; Michael Tunstall; William P. Marnane (SiPS, 2014)

Accelerating integer-based fully homomorphic encryption using Comba multiplication. - Ciara Moore; Máire O'Neill; Neil Hanley; Elizabeth O'Sullivan (SiPS, 2014)

Can leakage models be more efficient? non-linear models in side channel attacks. - Qizhi Tian; Máire O'Neill; Neil Hanley (WIFS, 2014)

Security Issues in QCA Circuit Design - Power Analysis Attacks. - Weiqiang Liu 001; Saket Srivastava; Máire O'Neill; Earl E. Swartzlander Jr. (Field-Coupled Nanocomputing, 2014)

On the Security of Balanced Encoding Countermeasures. - Yoo-Seung Won; Philip Hodgers; Máire O'Neill; Dong-Guk Han (CARDIS, 2015)

Neural network based attack on a masked implementation of AES. - Richard Gilmore; Neil Hanley; Máire O'Neill (HOST, 2015)

Ultra-compact and robust FPGA-based PUF identification generator. - Chongyan Gu; Máire O'Neill (ISCAS, 2015)

Pre-processing power traces to defeat random clocking countermeasures. - Philip Hodgers; Neil Hanley; Máire O'Neill (ISCAS, 2015)

RO PUF design in FPGAs with new comparison strategies. - Weiqiang Liu 001; Yifei Yu; Chenghua Wang; Yijun Cui; Máire O'Neill (ISCAS, 2015)

An Improved Second-Order Power Analysis Attack Based on a New Refined Expecter - - Case Study on Protected AES -. - Hyunjin Ahn; Neil Hanley; Máire O'Neill; Dong-Guk Han (WISA, 2015)

Security Analysis on RFID Mutual Authentication Protocol. - You Sung Kang; Elizabeth O'Sullivan; Dooho Choi; Máire O'Neill (WISA, 2015)

Improving RO PUF design using frequency distribution characteristics. - Yifei Yu; Chenghua Wang; Weiqiang Liu 001; Yijun Cui; Máire O'Neill (IEICE Electron. Express, 2015)

Privacy region protection for H.264/AVC with enhanced scrambling effect and a low bitrate overhead. - Yongsheng Wang; Máire O'Neill; Fatih Kurugollu; Elizabeth O'Sullivan (Signal Process. Image Commun., 2015)

Practical Lattice-Based Digital Signature Schemes. - James Howe; Thomas Pöppelmann; Máire O'Neill; Elizabeth O'Sullivan; Tim Güneysu (ACM Trans. Embed. Comput. Syst., 2015)

Introduction for Embedded Platforms for Cryptography in the Coming Decade. - Patrick Schaumont; Máire O'Neill; Tim Güneysu (ACM Trans. Embed. Comput. Syst., 2015)

Secure architectures of future emerging cryptography SAFEcrypto. - Máire O'Neill; Elizabeth O'Sullivan; Gavin McWilliams; Markku-Juhani O. Saarinen; Ciara Moore; Ayesha Khalid; James Howe; Rafaël Del Pino; Michel Abdalla; Francesco Regazzoni 001; Felipe Valencia; Tim Güneysu; et al. (Conf. Computing Frontiers, 2016)

Standard lattices in hardware. - James Howe; Ciara Moore; Máire O'Neill; Francesco Regazzoni 001; Tim Güneysu; K. Beeden (DAC, 2016)

Time-independent discrete Gaussian sampling for post-quantum cryptography. - Ayesha Khalid; James Howe; Ciara Rafferty; Máire O'Neill (FPT, 2016)

Live demonstration: An automatic evaluation platform for physical unclonable function test. - Yijun Cui; Chenghua Wang; Weiqiang Liu 001; Máire O'Neill (ISCAS, 2016)

Low-cost configurable ring oscillator PUF with improved uniqueness. - Yijun Cui; Chenghua Wang; Weiqiang Liu 001; Yifei Yu; Máire O'Neill; Fabrizio Lombardi (ISCAS, 2016)

Lattice-based cryptography: From reconfigurable hardware to ASIC. - Tobias Oder; Tim Güneysu; Felipe Valencia; Ayesha Khalid; Máire O'Neill; Francesco Regazzoni 001 (ISIC, 2016)

A Reconfigurable Memory PUF Based on Tristate Inverter Arrays. - Yijun Cui; Chenghua Wang; Weiqiang Liu 001; Máire O'Neill (SiPS, 2016)

Novel lightweight FF-APUF design for FPGA. - Chongyan Gu; Yijun Cui; Neil Hanley; Máire O'Neill (SoCC, 2016)

Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption. - Xiaolin Cao; Ciara Moore; Máire O'Neill; Elizabeth O'Sullivan; Neil Hanley (IEEE Trans. Computers, 2016)

Design and Analysis of Inexact Floating-Point Adders. - Weiqiang Liu 001; Linbin Chen; Chenghua Wang; Máire O'Neill; Fabrizio Lombardi (IEEE Trans. Computers, 2016)

Guest Editorial: New Frontiers in Signal Processing Applications and Embedded Processing Technologies. - John McAllister; Máire O'Neill; Maxime Pelcat (J. Signal Process. Syst., 2016)

FPGA-based strong PUF with increased uniqueness and entropy properties. - Chongyan Gu; Neil Hanley; Máire O'Neill (ISCAS, 2017)

Compact and provably secure lattice-based signatures in hardware. - James Howe; Ciara Rafferty; Ayesha Khalid; Máire O'Neill (ISCAS, 2017)

XOR gate based low-cost configurable RO PUF. - Lei Zhang 089; Chenghua Wang; Weiqiang Liu 001; Máire O'Neill; Fabrizio Lombardi (ISCAS, 2017)

GLITCH: A Discrete Gaussian Testing Suite For Lattice-Based Cryptography. - James Howe; Máire O'Neill (IACR Cryptol. ePrint Arch., 2017)

Evaluation of Large Integer Multiplication Methods on Hardware. - Ciara Rafferty; Máire McLoone; Neil Hanley (IEEE Trans. Computers, 2017)

Guest Editorial: Introduction to the Special Issue on Emerging Technologies and Designs for Application-Specific Computing. - Weiqiang Liu 001; Earl E. Swartzlander Jr.; Máire O'Neill (IEEE Trans. Emerg. Top. Comput., 2017)

Improved Reliability of FPGA-Based PUF Identification Generator Design. - Chongyan Gu; Neil Hanley; Máire O'Neill (ACM Trans. Reconfigurable Technol. Syst., 2017)

Approximate Computing and Its Application to Hardware Security. - Weiqiang Liu 001; Chongyan Gu; Gang Qu 001; Máire O'Neill (Cyber-Physical Systems Security, 2018)

Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography. - Sailong Fan; Weiqiang Liu 001; James Howe; Ayesha Khalid; Máire O'Neill (APCCAS, 2018)

Attacking Arbiter PUFs Using Various Modeling Attack Algorithms: A Comparative Study. - Yue Fang; Chenghua Wang; Qingqing Ma; Chongyan Gu; Máire O'Neill; Weiqiang Liu 001 (APCCAS, 2018)

Error Samplers for Lattice-Based Cryptography -Challenges, Vulnerabilities and Solutions. - Ayesha Khalid; Ciara Rafferty; James Howe; Séamus Brannigan; Weiqiang Liu 001; Máire O'Neill (APCCAS, 2018)

A machine learning attack resistant multi-PUF design on FPGA. - Qingqing Ma; Chongyan Gu; Neil Hanley; Chenghua Wang; Weiqiang Liu 001; Máire O'Neill (ASP-DAC, 2018)

Physical Protection of Lattice-Based Cryptography: Challenges and Solutions. - Ayesha Khalid; Tobias Oder; Felipe Valencia; Máire O'Neill; Tim Güneysu; Francesco Regazzoni 001 (ACM Great Lakes Symposium on VLSI, 2018)

Modelling Attack Analysis of Configurable Ring Oscillator (CRO) PUF Designs. - Jack Miskelly; Chongyan Gu; Qingqing Ma; Yijun Cui; Weiqiang Liu 001; Máire O'Neill (DSP, 2018)

Design and Optimization of Modular Multiplication for SIDH. - Chunyang Liu; Jian Ni; Weiqiang Liu 001; Zhe Liu 001; Máire O'Neill (ISCAS, 2018)

Design of Majority Logic (ML) Based Approximate Full Adders. - Tingting Zhang; Weiqiang Liu 001; Emma McLarnon; Máire O'Neill; Fabrizio Lombardi (ISCAS, 2018)

Addressing Side-Channel Vulnerabilities in the Discrete Ziggurat Sampler. - Séamus Brannigan; Máire O'Neill; Ayesha Khalid; Ciara Rafferty (SPACE, 2018)

Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design. - Yijun Cui; Chongyan Gu; Chenghua Wang; Máire O'Neill; Weiqiang Liu 001 (IEEE Access, 2018)

Compact, Scalable, and Efficient Discrete Gaussian Samplers for Lattice-Based Cryptography. - Ayesha Khalid; James Howe; Ciara Rafferty; Francesco Regazzoni 001; Máire O'Neill (IACR Cryptol. ePrint Arch., 2018)

On Practical Discrete Gaussian Samplers for Lattice-Based Cryptography. - James Howe; Ayesha Khalid; Ciara Rafferty; Francesco Regazzoni 001; Máire O'Neill (IEEE Trans. Computers, 2018)

Data Compression Device Based on Modified LZ4 Algorithm. - Weiqiang Liu 001; Faqiang Mei; Chenghua Wang; Máire O'Neill; Earl E. Swartzlander Jr. (IEEE Trans. Consumer Electron., 2018)

A Modeling Attack Resistant Deception Technique for Securing PUF based Authentication. - Chongyan Gu; Chip-Hong Chang; Weiqiang Liu 001; Shichao Yu; Qingqing Ma; Máire O'Neill (AsianHOST, 2019)

A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs. - Chongyan Gu; Chip-Hong Chang; Weiqiang Liu 001; Neil Hanley; Jack Miskelly; Máire O'Neill (ASHES@CCS, 2019)

Theoretical Analysis of Delay-Based PUFs and Design Strategies for Improvement. - Yale Wang; Chenghua Wang; Chongyan Gu; Yijun Cui; Máire O'Neill; Weiqiang Liu 001 (ISCAS, 2019)

Multi-Incentive Delay-Based (MID) PUF. - Zhengran Zhang; Chongyan Gu; Yijun Cui; Chuan Zhang 001; Máire O'Neill; Weiqiang Liu 001 (ISCAS, 2019)

An Improved Automatic Hardware Trojan Generation Platform. - Shichao Yu; Weiqiang Liu 001; Máire O'Neill (ISVLSI, 2019)

Lattice-based Cryptography for IoT in A Quantum World: Are We Ready? - Ayesha Khalid; Sarah McCarthy; Weiqiang Liu 001; Máire O'Neill (IACR Cryptol. ePrint Arch., 2019)

BEARZ Attack FALCON: Implementation Attacks with Countermeasures on the FALCON signature scheme. - Sarah McCarthy; James Howe; Neil Smyth; Séamus Brannigan; Máire O'Neill (IACR Cryptol. ePrint Arch., 2019)

A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations. - Chongyan Gu; Weiqiang Liu 001; Neil Hanley; Robert Hesselbarth; Máire O'Neill (IEEE Trans. Computers, 2019)

Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman. - Weiqiang Liu 001; Jian Ni; Zhe Liu 001; Chunyang Liu; Máire O'Neill (IEEE Trans. Computers, 2019)

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security. - Weiqiang Liu 001; Lei Zhang 089; Zhengran Zhang; Chongyan Gu; Chenghua Wang; Máire O'Neill; Fabrizio Lombardi (ACM Trans. Embed. Comput. Syst., 2019)

Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA. - Weiqiang Liu 001; Sailong Fan; Ayesha Khalid; Ciara Rafferty; Máire O'Neill (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Secure Algorithm for Rounded Gaussian Sampling. - Séamus Brannigan; Máire O'Neill; Ayesha Khalid; Ciara Rafferty (CANS, 2020)

Security Analysis of Hardware Trojans on Approximate Circuits. - Yuqin Dou; Shichao Yu; Chongyan Gu; Máire O'Neill; Chenghua Wang; Weiqiang Liu 001 (ACM Great Lakes Symposium on VLSI, 2020)

Programmable Ring Oscillator PUF Based on Switch Matrix. - Yijun Cui; Yunpeng Chen; Chenghua Wang; Chongyan Gu; Máire O'Neill; Weiqiang Liu 001 (ISCAS, 2020)

AxMM: Area and Power Efficient Approximate Modular Multiplier for R-LWE Cryptosystem. - Dur-e-Shahwar Kundi; Song Bian 001; Ayesha Khalid; Chenghua Wang; Máire O'Neill; Weiqiang Liu 001 (ISCAS, 2020)

A Novel Feature Extraction Strategy for Hardware Trojan Detection. - Shichao Yu; Chongyan Gu; Weiqiang Liu 001; Máire O'Neill (ISCAS, 2020)

Ten years of hardware Trojans: a survey from the attacker's perspective. - Mingfu Xue; Chongyan Gu; Weiqiang Liu 001; Shichao Yu; Máire O'Neill (IET Comput. Digit. Tech., 2020)

Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities. - Weiqiang Liu 001; Chongyan Gu; Máire O'Neill; Gang Qu 001; Paolo Montuschi; Fabrizio Lombardi (Proc. IEEE, 2020)

High Performance Modular Multiplication for SIDH. - Weiqiang Liu 001; Ziying Ni; Jian Ni; Ciara Rafferty; Máire O'Neill (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Fast DRAM PUFs on Commodity Devices. - Jack Miskelly; Máire O'Neill (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3. - Dur-e-Shahwar Kundi; Ayesha Khalid; Arshad Aziz; Chenghua Wang; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Circuits Syst., 2020)

An Efficient and Parallel R-LWE Cryptoprocessor. - Yuqing Zhang; Chenghua Wang; Dur-e-Shahwar Kundi; Ayesha Khalid; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Plaintext: A Missing Feature for Enhancing the Power of Deep Learning in Side-Channel Analysis? Breaking multiple layers of side-channel countermeasures. - Anh-Tuan Hoang; Neil Hanley; Máire O'Neill (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020)

High-Performance Systolic Array Montgomery Multiplier for SIKE. - Ziying Ni; Dur-e-Shahwar Kundi; Máire O'Neill; Weiqiang Liu 001 (ISCAS, 2021)

Towards CRYSTALS-Kyber: A M-LWE Cryptoprocessor with Area-Time Trade-Off. - Kan Yao; Dur-e-Shahwar Kundi; Chenghua Wang; Máire O'Neill; Weiqiang Liu 001 (ISCAS, 2021)

A Dynamic Highly Reliable SRAM-Based PUF Retaining Memory Function. - Hu Zhang; Chenghua Wang; Chenggang Yan 002; Yijun Cui; Chongyan Gu; Máire O'Neill; Weiqiang Liu 001 (ISCAS, 2021)

A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs. - Chongyan Gu; Chip-Hong Chang; Weiqiang Liu 001; Neil Hanley; Jack Miskelly; Máire O'Neill (J. Cryptogr. Eng., 2021)

DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices. - Ioannis Tsiokanos; Jack Miskelly; Chongyan Gu; Máire O'Neill; Georgios Karakonstantis (ACM J. Emerg. Technol. Comput. Syst., 2021)

A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication. - Chongyan Gu; Chip-Hong Chang; Weiqiang Liu 001; Shichao Yu; Yale Wang; Máire O'Neill (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation. - Chongyan Gu; Weiqiang Liu 001; Yijun Cui; Neil Hanley; Máire O'Neill; Fabrizio Lombardi (IEEE Trans. Emerg. Top. Comput., 2021)

Design and Analysis of Majority Logic-Based Approximate Adders and Multipliers. - Weiqiang Liu 001; Tingting Zhang; Emma McLarnon; Máire O'Neill; Paolo Montuschi; Fabrizio Lombardi (IEEE Trans. Emerg. Top. Comput., 2021)

Security Vulnerabilities and Countermeasures for Approximate Circuits. - Chongyan Gu; Yuqin Dou; Weiqiang Liu 001; Máire O'Neill (Approximate Computing, 2022)

Better Security Estimates for Approximate, IoT-Friendly R-LWE Cryptosystems. - Ruth O'Connor; Ayesha Khalid; Máire O'Neill; Weiqiang Liu 001 (APCCAS, 2022)

HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU. - Pengzhou He; Yazheng Tu; Ayesha Khalid; Máire O'Neill; Jiafeng Xie (DFT, 2022)

Acceleration of Post Quantum Digital Signature Scheme CRYSTALS-Dilithium on Reconfigurable Hardware. - Donal Campbell; Ciara Rafferty; Ayesha Khalid; Máire O'Neill (FPL, 2022)

High Performance FPGA-based Post Quantum Cryptography Implementations. - Ziying Ni; Ayesha Khalid; Máire O'Neill (FPL, 2022)

Stacked Ensemble Models Evaluation on DL Based SCA. - Anh-Tuan Hoang; Neil Hanley; Ayesha Khalid; Dur-e-Shahwar Kundi; Máire O'Neill (ICSBT/SECRYPT (Revised Selected Papers), 2022)

Stacked Ensemble Model for Enhancing the DL based SCA. - Anh-Tuan Hoang; Neil Hanley; Ayesha Khalid; Dur-e-Shahwar Kundi; Máire O'Neill (SECRYPT, 2022)

Efficient Pipelining Exploration for A High-performance CRYSTALS-Kyber Accelerator. - Ziying Ni; Ayesha Khalid; Dur-e-Shahwar Kundi; Máire O'Neill; Weiqiang Liu 001 (IACR Cryptol. ePrint Arch., 2022)

AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications. - Dur-e-Shahwar Kundi; Ayesha Khalid; Song Bian 001; Chenghua Wang; Máire O'Neill; Weiqiang Liu 001 (IEEE Internet Things J., 2022)

Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms. - Shanshan Liu 001; Bi Wu; Ke Chen 018; Weiqiang Liu 001; Máire O'Neill; Fabrizio Lombardi (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A High Performance SIKE Accelerator With High Frequency and Low Area-Time Product. - Ziying Ni; Dur-e-Shahwar Kundi; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs. - Dur-e-Shahwar Kundi; Yuqing Zhang; Chenghua Wang; Ayesha Khalid; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Emerg. Top. Comput., 2022)

A Dynamically Configurable PUF and Dynamic Matching Authentication Protocol. - Yale Wang; Chenghua Wang; Chongyan Gu; Yijun Cui; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Emerg. Top. Comput., 2022)

Deep Learning-Based Hardware Trojan Detection With Block-Based Netlist Information Extraction. - Shichao Yu; Chongyan Gu; Weiqiang Liu 001; Máire O'Neill (IEEE Trans. Emerg. Top. Comput., 2022)

A High-Performance SIKE Hardware Accelerator. - Ziying Ni; Dur-e-Shahwar Kundi; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs. - Yale Wang; Chenghua Wang; Chongyan Gu; Yijun Cui; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Towards a Lightweight CRYSTALS-Kyber in FPGAs: an Ultra-lightweight BRAM-free NTT Core. - Ziying Ni; Ayesha Khalid; Weiqiang Liu 001; Máire O'Neill (ISCAS, 2023)

Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators. - Safiullah Khan; Ayesha Khalid; Ciara Rafferty; Yasir Ali Shah; Máire O'Neill; Wai-Kong Lee; Seong Oun Hwang (VLSI-SoC, 2023)

HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining. - Ziying Ni; Ayesha Khalid; Dur-e-Shahwar Kundi; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Computers, 2023)

A Novel FPGA Mutually Coupled Configurable Ring Oscillator PUF. - James Moore; Jack Miskelly; Máire O'Neill; Chongyan Gu (AsianHOST, 2024)

Bitstream Fault Injection Attacks on CRYSTALS Kyber Implementations on FPGAs. - Ziying Ni; Ayesha Khalid; Weiqiang Liu 001; Máire O'Neill (DATE, 2024)

A Novel Methodology for Processor based PUF in Approximate Computing. - Aditya Japa; Jack Miskelly; Yijun Cui; Máire O'Neill; Chongyan Gu (ISCAS, 2024)

FPGA Bitstream Fault Injection Attack and Countermeasures on the Sampling Counter in CRYSTALS Kyber. - Ziying Ni; Ayesha Khalid; Weiqiang Liu 001; Máire O'Neill (ISCAS, 2024)

Efficient Soft Core Multiplier for Post Quantum Digital Signatures. - Yasir Ali Shah; Ciara Rafferty; Ayesha Khalid; Safiullah Khan; Khalid Javeed; Máire O'Neill (ISCAS, 2024)

Deep Learning Enhanced Side Channel Analysis on CRYSTALS-Kyber. - Anh-Tuan Hoang; Mark Kennaway; Dung Tuan Pham; Son Thai Mai; Ayesha Khalid; Ciara Rafferty; Máire O'Neill (ISQED, 2024)

Quantum-Safe HIBE: Does It Cost a Latte? - Raymond K. Zhao; Sarah McCarthy; Ron Steinfeld; Amin Sakzad; Máire O'Neill (IEEE Trans. Inf. Forensics Secur., 2024)

An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA. - Yijun Cui; Jiang Li 012; Yunpeng Chen; Chenghua Wang; Chongyan Gu; Máire O'Neill; Weiqiang Liu 001 (ACM Trans. Design Autom. Electr. Syst., 2024)

Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography. - Malik Imran; Safiullah Khan; Ayesha Khalid; Ciara Rafferty; Yasir Ali Shah; Samuel Pagliarini; Muhammad Rashid 001; Máire O'Neill (IEEE Embed. Syst. Lett., 2024)

AxRA: Approximate Rowhammer Attack for Modern DRAM Systems. - Yuhang Hao; Yun Wu 003; Ziying Ni; Jack Miskelly; Máire O'Neill; Chongyan Gu (ISCAS, 2025)

Kyber-KEM-Ascon: Benchmarking a Lightweight Post-quantum KEM on IoT Devices. - Sahar Shehzadi; Nathan Whaley; Ayesha Khalid; Abdul Ghafoor; Sadiqa Arshad; Faiz Ul Islam; Máire O'Neill (ISCAS, 2025)

An Enhanced Two-Step CPA Side-Channel Analysis Attack on ML-KEM. - Mark Kennaway; Anh-Tuan Hoang; Ayesha Khalid; Ciara Rafferty; Máire O'Neill (SECRYPT, 2025)

HRaccoon: A High-performance Configurable SCA Resilient Raccoon Hardware Accelerator. - Ziying Ni; Ayesha Khalid; Zhaoyu Zhang; Yijun Cui; Weiqiang Liu 001; Máire O'Neill (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

A Highly Hardware Efficient ML-KEM Accelerator with Optimised Architectural Layers. - Ziying Ni; Ayesha Khalid; Weiqiang Liu 001; Máire O'Neill (ACM Trans. Embed. Comput. Syst., 2025)