A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element. - Maitham Shams; Jo C. Ebergen; Mohamed I. Elmasry (ISLPED, 1996)

Optimizing CMOS Implementations of the C-element. - Maitham Shams; Jo C. Ebergen; Mohamed I. Elmasry (ICCD, 1997)

Modeling and comparing CMOS implementations of the C-element. - Maitham Shams; Jo C. Ebergen; Mohamed I. Elmasry (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions. - Maitham Shams; Mohamed I. Elmasry (ICCD, 1999)

A formulation for quick evaluation and optimization of digital CMOS circuits. - Maitham Shams; Mohamed I. Elmasry (ISCAS (6), 1999)

A unified delay model for CMOS logic styles. - Maitham Shams (ICECS, 2003)

Implementation of MCML universal logic gate for 10 GHz-range in 0.13 µm CMOS technology. - Shahnam Khabiri; Maitham Shams (ISCAS (2), 2004)

Multi-GHz energy-efficient asynchronous pipelined circuits in MOS Current Mode Logic. - Tin Wai Kwan; Maitham Shams (ISCAS (2), 2004)

Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic. - Tin Wai Kwan; Maitham Shams (ASYNC, 2005)

An MCML four-bit ripple-carry adder design in 1 GHz range. - Shahnam Khabiri; Maitham Shams (ISCAS (2), 2005)

A mathematical programming approach to designing MOS current-mode logic circuits. - Shahnam Khabiri; Maitham Shams (ISCAS (3), 2005)

Delay modeling of CMOS/CPL logic circuits. - Yuanzhong Wan; Maitham Shams (ISCAS (6), 2005)

Charge-Recovery Power Clock Generators for Adiabatic Logic Circuits. - Muhammad Arsalan; Maitham Shams (VLSI Design, 2005)

Design of Multi-GHz Asynchronous Pipelined Circuits in MOS Current-Mode Logic. - Tin Wai Kwan; Maitham Shams (VLSI Design, 2005)

Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder. - Yuanzhong Wan; Maitham Shams (VLSI Design, 2005)

Design and Analysis of A Class-E Frequency-Controlled Transcutaneous Energy Transfer System. - Ahmad Mizannojehdehi; Maitham Shams; Tofy Mussivand (ICECS, 2006)

A symmetric mos current-mode logic universal gate for high speed applications. - Osman Musa Abdulkarim; Maitham Shams (ACM Great Lakes Symposium on VLSI, 2007)

Asynchronous Adiabatic Logic. - Muhammad Arsalan; Maitham Shams (ISCAS, 2007)

Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies. - Raghid Shreih; Maitham Shams (ACM Great Lakes Symposium on VLSI, 2008)

Wireless Dosimeter: System-on-Chip Versus System-in-Package for Biomedical and Space Applications. - Atif Shamim; Muhammad Arsalan; Langis Roy; Maitham Shams; Nicolas G. Tarr (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

An Efficient Delay Model for MOS Current-Mode Logic Automated Design and Optimization. - Osman Musa Abdulkarim; Maitham Shams (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A simple and effective fluidic encapsulation protocol for bioMEMS devices. - Bashir I. Morshed; Maitham Shams; Tofy Mussivand (IEICE Electron. Express, 2011)

Preference of designing CMOS subthreshold logic circuits using uniform-size transistors. - Manmit Muker; Maitham Shams (IEICE Electron. Express, 2011)

Ultra Low Power CMOS-Based Sensor for On-Body Radiation Dose Measurements. - Muhammad Arsalan; Atif Shamim; Maitham Shams; Nicolas G. Tarr; Langis Roy (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

A gate sizing and transistor fingering strategy for subthreshold CMOS circuits. - Morteza Nabavi; Maitham Shams (IEICE Electron. Express, 2012)

Analysis of Electric Fields inside Microchannels and Single Cell Electrical Lysis with a Microfluidic Device. - Bashir I. Morshed; Maitham Shams; Tofy Mussivand (Micromachines, 2013)

Investigation of Low-Voltage Pulse Parameters on Electroporation and Electrical Lysis Using a Microfluidic Device With Interdigitated Electrodes. - Bashir I. Morshed; Maitham Shams; Tofy Mussivand (IEEE Trans. Biomed. Eng., 2014)

Single-ended 6T sub-threshold SRAM with horizontal local bit-lines. - Sukneet Basuta; Maitham Shams (MWSCAS, 2015)

Comprehensive investigation of gate oxide short in FinFETs. - Roya Dibaj; Dhamin Al-Khalili; Maitham Shams (VTS, 2017)

Temperature Independent Subthreshold Circuits Design. - Morteza Nabavi; Maitham Shams; Mohamad Sawan (ISOCC, 2018)

Gate Oxide Short Defect Model in FinFETs. - Roya Dibaj; Dhamin Al-Khalili; Maitham Shams (J. Electron. Test., 2018)

FinFET 6T-SRAM Compute-in-Memory Targeting Low Power Neural Networks Operations. - Waqas Gul; Maitham Shams; Dhamin Al-Khalili (ISCAS, 2023)