Majid Zamani

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Known people with the same name:

Bibliography

2023
DeepNav: Joint View Learning for Direct Optimal Path Perception in Cochlear Surgical Platform Navigation.
IEEE Access, 2023

A Deep Neural Network-Based Spike Sorting With Improved Channel Selection and Artefact Removal.
IEEE Access, 2023

2022
Generation of Anatomically Inspired Human Airway Tree Using Electrical Impedance Tomography: A Method to Estimate Regional Lung Filling Characteristics.
IEEE Trans. Medical Imaging, 2022

Insertion Guidance Based on Impedance Measurements of a Cochlear Electrode Array.
Frontiers Comput. Neurosci., 2022

A Compact CNN-Based Speech Enhancement With Adaptive Filter Design Using Gabor Function and Region-Aware Convolution.
IEEE Access, 2022

Efficient Approximation of Action Potentials with High-Order Shape Preservation in Unsupervised Spike Sorting.
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022

2021
Towards More Efficient DNN-Based Speech Enhancement Using Quantized Correlation Mask.
IEEE Access, 2021

A Discrete Wavelet Transform-Based Voice Activity Detection and Noise Classification with Sub-Band Selection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Accurate, Very Low Computational Complexity Spike Sorting Using Unsupervised Matched Subspace Learning.
IEEE Trans. Biomed. Circuits Syst., 2020

A Fast and Reliable Three-Dimensional Centerline Tracing: Application to Virtual Cochlear Implant Surgery.
IEEE Access, 2020

Adaptive Electrical Impedance Tomography Resolution Enhancement Using Statistically Quantized Projected Image Sub-Bands.
IEEE Access, 2020

2018
An Adaptive Neural Spike Processor With Embedded Active Learning for Improved Unsupervised Sorting Accuracy.
IEEE Trans. Biomed. Circuits Syst., 2018

2017
A highly accurate spike sorting processor with reconfigurable embedded frames for unsupervised and adaptive analysis of neural signals.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2015
Power optimization of neural frontend interfaces.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A feature design framework for hardware efficient neural spike sorting.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

Patient specific Parkinson's disease detection for adaptive deep brain stimulation.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

2013
Erratum: "an Energy Efficient Second-Order σδ modulator Based on the Power and Delay Optimization of CBSC IIR filter".
J. Circuits Syst. Comput., 2013

Analog-to-digital converters power dissipation limits of CBSC-based pipelined.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Dimensionality reduction using asynchronous sampling of first derivative features for real-time and computationally efficient neural spike sorting.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Suitable compensation circuits for on-chip interference reduction in neural tripolar recordings.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
Control of cyber-physical systems using incremental properties of physical systems.
PhD thesis, 2012

An Energy Efficient Second-Order σδ modulator Based on the Power and Delay Optimization of CBSC IIR filter.
J. Circuits Syst. Comput., 2012

CBSC-based pipelined analog-to-digital converters: Power dissipation bound analysis.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Performance comparison of artificial intelligence networks in nanoscale MOSFET modeling.
Proceedings of the Seventh International Conference on Natural Computation, 2011

A fourth-order, low-pass, MASH ΔΣ modulator with CBSC technique in 0.18μm CMOS.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

Efficient parameters selection for artificial intelligence models of nanoscale MOSFETs.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2010
A12b, 40-MS/s, 4.1mW fully differential CBSC pipelined ADC in 0.18µm CMOS.
IEICE Electron. Express, 2010

A10b, 20-MS/s, 2.6mW fully differential CBSC pipelined ADC in 0.18µm CMOS.
IEICE Electron. Express, 2010


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