A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operation. - Tsuguo Kobayashi; Kazutaka Nogami; Tsukasa Shirotori; Yukihiro Fujimoto; Yoshitaka Biwaki; Haruo Nohara; Makiji Kobayashi; Kiyoshi Kobayashi; Kazuhiro Sawada (IEEE J. Solid State Circuits, 1991)