A CMOS gate array with 600 Mb/s simultaneous bidirectional I/O circuits. - Toshiro Takahashi; Makio Uchida; Takahiko Takahashi; Ryozo Yoshino; Masakazu Yamamoto; Nobuh Kitamura (IEEE J. Solid State Circuits, 1995)

Switching well noise analysis and minimization strategy for low Vth CMOS integrated circuits. - Akio Koyama; Masatoshi Tsuge; Jun'ya Kudo; Tatsuhiro Aida; Makio Uchida (CICC, 1999)

Switching well noise modeling and minimization strategy for digitalcircuits with a controllable threshold voltage scheme. - Akio Koyama; Makio Uchida; Tatsuhiro Aida; Jun'ya Kudo; Masatoshi Tsuge (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)