A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC. - Jun Deguchi; Fumihiko Tachibana; Makoto Morimoto; Masayoshi Chiba; Takeshi Miyaba; Hideki Tanaka; Kyoichi Takenaka; Satoshi Funayama; Kunihiko Amano; Kazuhide Sugiura; Ryuta Okamoto; Shouhei Kousai (ISSCC, 2013)

A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication. - Jun Deguchi; Toshiyuki Yamagishi; Hideaki Majima; Nau Ozaki; Kazuhiro Hiwada; Makoto Morimoto; Tatsuji Ashitani; Shouhei Kousai (A-SSCC, 2014)

A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems. - Yuta Tsubouchi; Daisuke Miyashita; Yuji Satoh; Takashi Toi; Fumihiko Tachibana; Makoto Morimoto; Junji Wadatsumi; Jun Deguchi (VLSI Circuits, 2018)

A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. - Takashi Toi; Junji Wadatsumi; Hiroyuki Kobayashi; Yutaka Shimizu; Yuji Satoh; Makoto Morimoto; Rui Ito; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Go Urakawa; Jun Deguchi (ISSCC, 2019)

A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems. - Yuta Tsubouchi; Daisuke Miyashita; Takashi Toi; Yuji Satoh; Fumihiko Tachibana; Junji Wadatsumi; Makoto Morimoto; Ryuichi Fujimoto; Jun Deguchi (IEEE J. Solid State Circuits, 2019)

A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. - Takashi Toi; Junji Wadatsumi; Hiroyuki Kobayashi; Yutaka Shimizu; Yuji Satoh; Makoto Morimoto; Rui Ito; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Go Urakawa; Jun Deguchi; et al. (IEEE J. Solid State Circuits, 2022)