A 29-ns 64-Mb DRAM with hierarchical array architecture. - Masayuki Nakamura; Tugio Takahashi; Takesada Akiba; Goro Kitsukawa; Makoto Morino; Toshihiro Sekiguchi; Isamu Asano; Katsuo Komatsuzaki; Yoshitaka Tadaki; Songsu Cho; Kazuhiko Kajigaya; Tadashi Tachibana; et al. (IEEE J. Solid State Circuits, 1996)

A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. - Tsugio Takahashi; Tomonori Sekiguchi; Riichiro Takemura; Seiji Narui; Hiroki Fujisawa; Shinichi Miyatake; Makoto Morino; Koji Arai; Satoru Yamada; Shoji Shukuri; Masayuki Nakamura; Yoshitaka Tadaki; et al. (IEEE J. Solid State Circuits, 2001)

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. - Tatsuya Matano; Yasuhiro Takai; Tsugio Takahashi; Yuusuke Sakito; Isamu Fujii; Yoshihiro Takaishi; Hiroki Fujisawa; Shuichi Kubouchi; Seiji Narui; Koji Arai; Makoto Morino; Masayuki Nakamura; et al. (IEEE J. Solid State Circuits, 2003)

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer. - Hiroki Fujisawa; Masayuki Nakamura; Yasuhiro Takai; Yasuji Koshikawa; Tatsuya Matano; Seiji Narui; Narikazu Usuki; Chiaki Dono; Shinichi Miyatake; Makoto Morino; Koji Arai; Shuichi Kubouchi; et al. (IEEE J. Solid State Circuits, 2005)