Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. - Hiroshi Ando; Takashi Morie; Makoto Nagata; Atsushi Iwata (ICONIP, 1998)

Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. - Souta Sakabayashi; Takashi Morie; Makoto Nagata; Atsushi Iwata (ICONIP, 1998)

A PWM signal processing core circuit based on a switched current integration technique. - Makoto Nagata; Jun Funakoshi; Atsushi Iwata (IEEE J. Solid State Circuits, 1998)

Measurements and analyses of substrate noise waveform in mixed signal IC environment. - Makoto Nagata; Yoji Kashima; Daisuke Tamura; Takashi Morie; Atsushi Iwata (CICC, 1999)

A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. - Atsushi Iwata; Makoto Nagata; Hiroyuki Nakamoto; Noriaki Takeda; Mitsuru Homma; Hiroto Higashi; Takashi Morie (VLSI, 1999)

An arbitrary chaos generator core curcuit using PWM/PPM signals. - Kenichi Murakoshi; Takashi Morie; Makoto Nagata; Atsushi Iwata (ASP-DAC, 2000)

Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial. - Makoto Nagata; Atsushi Iwata (ASP-DAC, 2000)

A smart imager for the vision processing front-END. - Noriaki Takeda; Mitsuru Homma; Makoto Nagata; Takashi Morie; Atsushi Iwata (ASP-DAC, 2000)

Quantitative characterization of substrate noise for physical design guides in digital circuits. - Makoto Nagata; Jin Nagai; Takashi Morie; Atsushi Iwata (CICC, 2000)

Pulse modulation circuit architecture and its application to functional image sensors. - Atsushi Iwata; Makoto Nagata; Noriaki Takeda; Mitsuru Homma; Takashi Morie (ISCAS, 2000)

Measurements and analyses of substrate noise waveform inmixed-signal IC environment. - Makoto Nagata; Jin Nagai; Takashi Morie; Atsushi Iwata (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Test circuits for substrate noise evaluation in CMOS digital ICs. - Makoto Nagata; Takafumi Ohmoto; Jin Nagai; Takashi Morie; Atsushi Iwata (ASP-DAC, 2001)

Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. - Yoshitaka Murasaka; Makoto Nagata; Takafumi Ohmoto; Takashi Morie; Atsushi Iwata (ISQED, 2001)

An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. - Takashi Morie; Tomohiro Matsuura; Makoto Nagata; Atsushi Iwata (NIPS, 2001)

A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution. - Shigeo Kinoshita; Takashi Morie; Makoto Nagata; Atsushi Iwata (IEEE J. Solid State Circuits, 2001)

Physical design guides for substrate noise reduction in CMOS digital circuits. - Makoto Nagata; Jin Nagai; Katsumasa Hijikata; Takashi Morie; Atsushi Iwata (IEEE J. Solid State Circuits, 2001)

A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. - Teppei Nakano; Takashi Morie; Makoto Nagata; Atsushi Iwata (APCCAS (2), 2002)

Modeling substrate noise generation in CMOS digital integrated circuits. - Makoto Nagata; Takashi Morie; Atsushi Iwata (CICC, 2002)

Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. - Makoto Nagata; Yoshitaka Murasaka; Youichi Nishimori; Takashi Morie; Atsushi Iwata (ASP-DAC/VLSI Design, 2002)

Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques. - Hiroshi Ando; Takashi Morie; Makoto Miyake; Makoto Nagata; Atsushi Iwata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A substrate noise analysis methodology for large-scale mixed-signal ICs. - Wen Kung Chu; Nishath K. Verghese; Heayn-Jun Chol; Kenji Shimazaki; Hiroyuki Tsujikawa; Shouzou Hirano; Shirou Doushoh; Makoto Nagata; Atsushi Iwata; Takafumi Ohmoto (CICC, 2003)

Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement. - Shen Lin; Makoto Nagata; Kenji Shimazaki; Kazuhiro Satoh; Masaya Sumita; Hiroyuki Tsujikawa; Andrew T. Yang (CICC, 2004)

Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias. - Yoshihide Komatsu; Koichiro Ishibashi; Masaharu Yamamoto; Toshiro Tsukada; Kenji Shimazaki; Mitsuya Fukazawa; Makoto Nagata (CICC, 2005)

An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs. - Kenji Shimazaki; Mitsuya Fukazawa; Makoto Nagata; Shingo Miyahara; Masaaki Hirata; Kazuhiro Satoh; Hiroyuki Tsujikawa (CICC, 2005)

On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits. - Koichiro Noguchi; Makoto Nagata (DATE, 2005)

An on-chip multi-channel waveform monitor for mixed-signal VLSI diagnostics. - Koichiro Noguchi; Makoto Nagata (ESSCIRC, 2005)

High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition. - Masao Morimoto; Makoto Nagata; Kazuo Taki (IEICE Trans. Electron., 2005)

Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition. - Masao Morimoto; Yoshinori Tanaka; Makoto Nagata; Kazuo Taki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits. - Kenji Shimazaki; Makoto Nagata; Takeshi Okumoto; Shozo Hirano; Hiroyuki Tsujikawa (IEICE Trans. Electron., 2005)

A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation. - Teppei Nakano; Takashi Morie; Makoto Nagata; Atsushi Iwata (J. Robotics Mechatronics, 2005)

A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits. - Makoto Nagata; Takeshi Okumoto; Kazuo Taki (IEEE J. Solid State Circuits, 2005)

A built-in power supply noise probe for digital LSIs. - Mitsuya Fukazawa; Koichiro Noguchi; Makoto Nagata; Kazuo Taki (ASP-DAC, 2006)

Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation. - Daisuke Kosaka; Makoto Nagata (ASP-DAC, 2006)

Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform. - Mitsuya Fukazawa; Makoto Nagata (CICC, 2006)

Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise. - Mitsuya Fukazawa; Makoto Nagata (IEICE Trans. Electron., 2006)

Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach. - Yohei Fukumizu; Makoto Nagata; Kazuo Taki (IEICE Trans. Electron., 2006)

Communication Scheme for a Highly Collision-Resistive RFID System. - Yohei Fukumizu; Shuji Ohno; Makoto Nagata; Kazuo Taki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Multi-Ported Register File for Reducing the Impact of PVT Variation. - Yuuichirou Ikeda; Masaya Sumita; Makoto Nagata (IEICE Trans. Electron., 2006)

An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity. - Koichiro Noguchi; Makoto Nagata (IEICE Trans. Electron., 2006)

An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs. - Kenji Shimazaki; Makoto Nagata; Mitsuya Fukazawa; Shingo Miyahara; Masaaki Hirata; Kazuhiro Satoh; Hiroyuki Tsujikawa (IEICE Trans. Electron., 2006)

Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation. - Ali Afzali-Kusha; Makoto Nagata; Nishath K. Verghese; David J. Allstot (Proc. IEEE, 2006)

Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation. - Daisuke Kosaka; Makoto Nagata; Yoshitaka Murasaka; Atsushi Iwata (CICC, 2007)

On-Chip Measurements Complementary to Design Flow for Integrity in SoCs. - Makoto Nagata (DAC, 2007)

Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs. - Mitsuya Fukazawa; Tetsuro Matsuno; Toshifumi Uemura; Rei Akiyama; Tetsuya Kagemoto; Hiroshi Makino; Hidehiro Takata; Makoto Nagata (ISSCC, 2007)

On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications. - Tomio Sato; Atsuki Inoue; Tetsuyoshi Shiota; Tomoko Inoue; Yukihito Kawabe; Tetsutaro Hashimoto; Toshifumi Imamura; Yoshitaka Murasaka; Makoto Nagata; Atsushi Iwata (ISSCC, 2007)

A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System. - Yohei Fukumizu; Naoki Gochi; Makoto Nagata; Kazuo Taki (IEICE Trans. Electron., 2007)

Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements. - Kouji Ichikawa; Yuki Takahashi; Makoto Nagata (IEICE Trans. Electron., 2007)

Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias. - Yoshihide Komatsu; Koichiro Ishibashi; Makoto Nagata (IEICE Trans. Electron., 2007)

Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits. - Daisuke Kosaka; Makoto Nagata; Yoshitaka Murasaka; Atsushi Iwata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Chip-Level Substrate Coupling Analysis with Reference Structures for Verification. - Daisuke Kosaka; Makoto Nagata; Yoshitaka Murasaka; Atsushi Iwata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations. - Masao Morimoto; Makoto Nagata; Kazuo Taki (IEICE Trans. Electron., 2007)

On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration. - Koichiro Noguchi; Takushi Hashida; Makoto Nagata (IEICE Trans. Electron., 2007)

An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. - Koichiro Noguchi; Makoto Nagata (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Session 13 - Biomedical, sensors and MEMS. - Makoto Nagata; Steven L. Garverick (CICC, 2008)

Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation. - Kouji Ichikawa; Yuki Takahashi; Yukihiko Sakurai; Takahiro Tsuda; Isao Iwase; Makoto Nagata (IEICE Trans. Electron., 2008)

Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications. - Takefumi Yoshikawa; Tetsuhiro Ogino; Makoto Nagata (IEICE Trans. Electron., 2008)

A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design. - Daisuke Kosaka; Yoji Bando; Goichi Yokomizo; Kunihiko Tsuboi; Ying Shiun Li; Shen Lin; Makoto Nagata (CICC, 2009)

A 6-bit arbitrary digital noise emulator in 65nm CMOS technology. - Tetsuro Matsuno; Daisuke Fujimoto; Daisuke Kosaka; Naoyuki Hamanishi; Ken Tanabe; Masazumi Shiochi; Makoto Nagata (CICC, 2009)

Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations. - Mitsuya Fukazawa; Masanori Kurimoto; Rei Akiyama; Hidehiro Takata; Makoto Nagata (IEICE Trans. Electron., 2009)

An on-chip waveform capturing technique pursuing minimum cost of integration. - Yuuki Araga; Takushi Hashida; Makoto Nagata (ISCAS, 2010)

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails. - Takushi Hashida; Makoto Nagata (IEICE Trans. Electron., 2010)

An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology. - Tetsuro Matsuno; Daisuke Fujimoto; Daisuke Kosaka; Naoyuki Hamanishi; Ken Tanabe; Masazumi Shiochi; Makoto Nagata (IEICE Trans. Electron., 2010)

Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits. - Tetsuro Matsuno; Daisuke Kosaka; Makoto Nagata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

In-tier diagnosis of power domains in 3D TSV ICs. - Yuuki Araga; Makoto Nagata; Geert Van der Plas; Jaemin Kim; Nikolaos Minas; Pol Marchal; Youssef Travaly; Michael Libois; Antonio La Manna; Wenqi Zhang; Eric Beyne (3DIC, 2011)

A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. - Daisuke Fujimoto; Makoto Nagata; Toshihiro Katashita; Akihiro T. Sasaki; Yohei Hori; Akashi Satoh (HOST, 2011)

Accurate analysis of substrate sensitivity of active transistors in an analog circuit. - Satoshi Takaya; Yoji Bando; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (ISQED, 2011)

A diagnosis testbench of analog IP cores against on-chip environmental disturbances. - Takushi Hashida; Yuuki Araga; Makoto Nagata (VTS, 2011)

Microprocessor power noise measurements with different levels of resource occupancy. - Yoji Bando; Makoto Nagata (IEICE Electron. Express, 2011)

A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits. - Yoji Bando; Satoshi Takaya; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2011)

A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength. - Takushi Hashida; Yuuki Araga; Makoto Nagata (IEICE Trans. Electron., 2011)

On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement. - Masaaki Souda; Yoji Bando; Satoshi Takaya; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2011)

An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration. - Takushi Hashida; Makoto Nagata (IEEE J. Solid State Circuits, 2011)

Foreword. - Ajith Amerasekera; Makoto Nagata (VLSIC, 2012)

On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors. - Yoji Bando; Satoshi Takaya; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2012)

Modeling and Analysis of Substrate Noise Coupling in Analog and RF ICs. - Makoto Nagata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation. - Takuya Sawada; Taku Toshikawa; Kumpei Yoshikawa; Hidehiro Takata; Koji Nii; Makoto Nagata (IEICE Trans. Electron., 2012)

Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits. - Kumpei Yoshikawa; Yuta Sasaki; Kouji Ichikawa; Yoshiyuki Saito; Makoto Nagata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits. - Makoto Nagata; Vivek De (IEEE J. Solid State Circuits, 2012)

Very low-voltage swing while high-bandwidth data transmission through 4096 bit TSVs. - Satoshi Takaya; Makoto Nagata; Hiroaki Ikeda (3DIC, 2013)

Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator. - Naoya Azuma; Shunsuke Shimazaki; Noriyuki Miura; Makoto Nagata; Tomomitsu Kitamura; Satoru Takahashi; Motoki Murakami; Kazuaki Hori; Atsushi Nakamura; Kenta Tsukamoto; Mizuki Iwanami; Eiji Hankui; et al. (EMC Compo, 2013)

Noise analysis using on-chip waveform monitor in bandgap voltage references. - Akitaka Murata; Shuji Agatsuma; Daisaku Ikoma; Kouji Ichikawa; Takahiro Tsuda; Makoto Nagata; Kumpei Yoshikawa; Yuuki Araga; Yuji Harada (EMC Compo, 2013)

In-band spurious attenuation in LTE-class RFIC chip using a soft magnetic thin film. - Sho Muroga; Y. Shimada; Yasushi Endo; Satoshi Tanaka; Masahiro Yamaguchi; Naoya Azuma; Makoto Nagata; Motoki Murakami; Kazuaki Hori; Satoru Takahashi (EMC Compo, 2013)

Measurement-based diagnosis of wireless communication performance in the presence of in-band interferers in RF ICs. - Makoto Nagata; Shunsuke Shimazaki; Naoya Azuma; Satoru Takahashi; Motoki Murakami; Kazuaki Hori; Satoshi Tanaka; Masahiro Yamaguchi (EMC Compo, 2013)

Immunity evaluation of inverter chains against RF power on power delivery network. - Kumpei Yoshikawa; Yuji Harada; Noriyuki Miura; Noriaki Takeda; Yoshiyuki Saito; Makoto Nagata (EMC Compo, 2013)

A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing. - Satoshi Takaya; Makoto Nagata; Atsushi Sakai; Takashi Kariya; Shiro Uchiyama; Harufumi Kobayashi; Hiroaki Ikeda (ISSCC, 2013)

In-system diagnosis of RF ICs for tolerance against on-chip in-band interferers. - Naoya Azuma; T. Makita; S. Ueyama; Makoto Nagata; Satoru Takahashi; Motoki Murakami; Kazuaki Hori; Satoshi Tanaka; Masahiro Yamaguchi (ITC, 2013)

Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring. - Yuuki Araga; Nao Ueda; Yasumasa Takagi; Makoto Nagata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Equivalent Circuit Representation of Silicon Substrate Coupling of Passive and Active RF Components. - Naoya Azuma; Makoto Nagata (IEICE Trans. Electron., 2013)

A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. - Daisuke Fujimoto; Toshihiro Katashita; Akihiko Sasaki; Yohei Hori; Akashi Satoh; Makoto Nagata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits. - Takeshi Okumoto; Kumpei Yoshikawa; Makoto Nagata (IEICE Trans. Electron., 2013)

Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation. - Satoshi Takaya; Yoji Bando; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2013)

An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor. - Noriyuki Miura; Daisuke Fujimoto; Rie Korenaga; Kohei Matsuda; Makoto Nagata (A-SSCC, 2014)

On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips. - Makoto Nagata; Daisuke Fujimoto; Noriyuki Miura (ATS, 2014)

Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. - Shivam Bhasin; Jean-Luc Danger; Tarik Graba; Yves Mathieu; Daisuke Fujimoto; Makoto Nagata (ES4CPS@DATE, 2014)

Side-channel leakage on silicon substrate of CMOS cryptographic chip. - Daisuke Fujimoto; Daichi Tanaka; Noriyuki Miura; Makoto Nagata; Yu-ichi Hayashi; Naofumi Homma; Shivam Bhasin; Jean-Luc Danger (HOST, 2014)

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. - Yohei Nakata; Yuta Kimi; Shunsuke Okumura; Jinwook Jung; Takuya Sawada; Taku Toshikawa; Makoto Nagata; Hirofumi Nakano; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Hiroyuki Kawai; et al. (ISQED, 2014)

12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. - Noriyuki Miura; Shiro Dosho; Satoshi Takaya; Daisuke Fujimoto; Takuya Kiriyama; Hiroyuki Tezuka; Takuji Miki; Hiroto Yanagawa; Makoto Nagata (ISSCC, 2014)

A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils. - Taisuke Hayashi; Noriyuki Miura; Kumpei Yoshikawa; Makoto Nagata (VLSI-DAT, 2014)

A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor. - Noriyuki Miura; Daisuke Fujimoto; Daichi Tanaka; Yu-ichi Hayashi; Naofumi Homma; Takafumi Aoki; Makoto Nagata (VLSIC, 2014)

EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor. - Naofumi Homma; Yu-ichi Hayashi; Noriyuki Miura; Daisuke Fujimoto; Daichi Tanaka; Makoto Nagata; Takafumi Aoki (IACR Cryptol. ePrint Arch., 2014)

Timing margin enhancement technique for current mode interface. - Takefumi Yoshikawa; Makoto Nagata (IEICE Electron. Express, 2014)

Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator. - Naoya Azuma; Shunsuke Shimazaki; Noriyuki Miura; Makoto Nagata; Tomomitsu Kitamura; Satoru Takahashi; Motoki Murakami; Kazuaki Hori; Atsushi Nakamura; Kenta Tsukamoto; Mizuki Iwanami; Eiji Hankui; et al. (IEICE Trans. Electron., 2014)

Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. - Daisuke Fujimoto; Noriyuki Miura; Makoto Nagata; Yu-ichi Hayashi; Naofumi Homma; Takafumi Aoki; Yohei Hori; Toshihiro Katashita; Kazuo Sakiyama; Thanh-Ha Le; Julien Bringer; Pirouz Bazargan-Sabet; et al. (IEICE Trans. Electron., 2014)

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. - Yohei Nakata; Yuta Kimi; Shunsuke Okumura; Jinwook Jung; Takuya Sawada; Taku Toshikawa; Makoto Nagata; Hirofumi Nakano; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Hiroyuki Kawai; et al. (IEICE Trans. Electron., 2014)

Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking. - Satoshi Takaya; Hiroaki Ikeda; Makoto Nagata (IEICE Trans. Electron., 2014)

AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model. - Kumpei Yoshikawa; Kouji Ichikawa; Makoto Nagata (IEICE Trans. Electron., 2014)

Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC). - Makoto Nagata; Lucien J. Breems; Carlo Samori; Sven Mattisson; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

Nano-Function materials for TSV technologies. - Hiroaki Ikeda; Shigenobu Sekine; Ryuji Kimura; Koichi Shimokawa; Keiji Okada; Hiroaki Shindo; Tatsuya Ooi; Rei Tamaki; Makoto Nagata (3DIC, 2015)

A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor. - Daisuke Fujimoto; Noriyuki Miura; Yu-ichi Hayashi; Naofumi Homma; Takafumi Aoki; Makoto Nagata (ASP-DAC, 2015)

A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement. - Daisuke Fujimoto; Makoto Nagata; Shivam Bhasin; Jean-Luc Danger (ASP-DAC, 2015)

EM attack sensor: concept, circuit, and design-automation methodology. - Noriyuki Miura; Daisuke Fujimoto; Makoto Nagata; Naofumi Homma; Yu-ichi Hayashi; Takafumi Aoki (DAC, 2015)

Analysis of on-chip digital noise coupling path for wireless communication IC test chip. - Satoshi Tanaka; Peng Fan; Jingyan Ma; Hanae Aoki; Masahiro Yamaguchi; Makoto Nagata; Sho Muroga (EMC Compo, 2015)

Optimal error feedback filters for uniform quantizers at remote sensors. - Shuichi Ohno; Yuji Wakasa; Makoto Nagata (ICASSP, 2015)

Session 20 overview: Energy harvesting and SC power conversion: Analog subcommittee. - Makoto Nagata; Stefano Stanzione (ISSCC, 2015)

At-Product-Test Dedicated Adaptive supply-resonance suppression. - Kohki Taniguchi; Noriyuki Miura; Taisuke Hayashi; Makoto Nagata (VTS, 2015)

In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking. - Makoto Nagata; Satoshi Takaya; Hiroaki Ikeda (IEEE Des. Test, 2015)

A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. - Noriyuki Miura; Shiro Dosho; Hiroyuki Tezuka; Takuji Miki; Daisuke Fujimoto; Takuya Kiriyama; Makoto Nagata (IEEE J. Solid State Circuits, 2015)

A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation. - Sho Endo; Yang Li 001; Naofumi Homma; Kazuo Sakiyama; Kazuo Ohta; Daisuke Fujimoto; Makoto Nagata; Toshihiro Katashita; Jean-Luc Danger; Takafumi Aoki (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference. - Takuya Sawada; Kumpei Yoshikawa; Hidehiro Takata; Koji Nii; Makoto Nagata (IEEE Trans. Very Large Scale Integr. Syst., 2015)

PLL to the rescue: a novel EM fault countermeasure. - Noriyuki Miura; Zakaria Najm; Wei He 015; Shivam Bhasin; Xuan Thuy Ngo; Makoto Nagata; Jean-Luc Danger (DAC, 2016)

A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. - Takuji Miki; Noriyuki Miura; Kento Mizuta; Shiro Dosho; Makoto Nagata (ESSCIRC, 2016)

Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection. - Wei He 015; Jakub Breier; Shivam Bhasin; Noriyuki Miura; Makoto Nagata (FDTC, 2016)

On-chip substrate-bounce monitoring for laser-fault countermeasure. - Kohei Matsuda; Noriyuki Miura; Makoto Nagata; Yu-ichi Hayashi; Tatsuya Fujii; Kazuo Sakiyama (AsianHOST, 2016)

F1: Designing secure systems: Manufacturing, circuits and architectures. - Vivek De; Kerry Bernstein; Takefumi Yoshikawa; Yusuf Leblebici; Marian Verhelst; Mahesh Mehendale; Makoto Nagata (ISSCC, 2016)

A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version). - Daisuke Fujimoto; Shivam Bhasin; Makoto Nagata; Jean-Luc Danger (IACR Cryptol. ePrint Arch., 2016)

An FPGA-compatible PLL-based sensor against fault injection attack. - Wei He 015; Jakub Breier; Shivam Bhasin; Noriyuki Miura; Makoto Nagata (ASP-DAC, 2017)

Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF. - Noriyuki Miura; Masanori Takahashi; Kazuki Nagatomo; Makoto Nagata (A-SSCC, 2017)

Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault Analysis. - Takeshi Sugawara 001; Natsu Shoji; Kazuo Sakiyama; Kohei Matsuda; Noriyuki Miura; Makoto Nagata (FDTC, 2017)

15.8 A permanent digital archive system based on 4F2 x-point multi-layer metal nano-dot structure. - Noriyuki Miura; Shijia Liu; Tsuyoshi Watanabe; Shigeki Imai; Makoto Nagata (ISSCC, 2017)

Protecting cryptographic integrated circuits with side-channel information. - Makoto Nagata; Daisuke Fujimoto; Noriyuki Miura; Naofumi Homma; Yu-ichi Hayashi; Kazuo Sakiyama (IEICE Electron. Express, 2017)

A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS. - Takuji Miki; Noriyuki Miura; Kento Mizuta; Shiro Dosho; Makoto Nagata (IEICE Trans. Electron., 2017)

Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks. - Naofumi Homma; Yu-ichi Hayashi; Noriyuki Miura; Daisuke Fujimoto; Makoto Nagata; Takafumi Aoki (J. Cryptol., 2017)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. - Jean-Luc Danger; Risa Yashiro; Tarik Graba; Yves Mathieu; Abdelmalek Si-Merabet; Kazuo Sakiyama; Noriyuki Miura; Makoto Nagata (DSD, 2018)

Session 21 overview: Extending silicon and its applications: Technology directions subcommittee. - Jan Genoe; Frederic Gianesello; Makoto Nagata (ISSCC, 2018)

A 286F2/cell distributed bulk-current sensor and secure flush code eraser against laser fault injection attack. - Kohei Matsuda; Tatsuya Fujii; Natsu Shoji; Takeshi Sugawara 001; Kazuo Sakiyama; Yu-ichi Hayashi; Makoto Nagata; Noriyuki Miura (ISSCC, 2018)

Session 17 overview: Technologies for health and society: Technology directions subcommittee. - Patrick P. Mercier; Long Yan; Makoto Nagata (ISSCC, 2018)

Session 30 overview: Emerging memories: Memory and technology directions subcommittees. - Shinichiro Shiratake; Edoardo Charbon; Leland Chang; Makoto Nagata (ISSCC, 2018)

Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees. - Naveen Verma; Fatih Hamzaoglu; Makoto Nagata; Leland Chang (ISSCC, 2018)

A study on substrate noise coupling among TSVs in 3D chip stack. - Yuuki Araga; Makoto Nagata; Joeri De Vos; Geert Van der Plas; Eric Beyne (IEICE Electron. Express, 2018)

A 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor. - Kohei Matsuda; Tatsuya Fujii; Natsu Shoji; Takeshi Sugawara 001; Kazuo Sakiyama; Yu-ichi Hayashi; Makoto Nagata; Noriyuki Miura (IEEE J. Solid State Circuits, 2018)

Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor. - Noriyuki Miura; Masanori Takahashi; Kazuki Nagatomo; Makoto Nagata (IEEE J. Solid State Circuits, 2018)

A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs. - Daisuke Fujimoto; Shota Nin; Yu-ichi Hayashi; Noriyuki Miura; Makoto Nagata; Tsutomu Matsumoto (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. - Takuji Miki; Makoto Nagata; Akihiro Tsukioka; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (3DIC, 2019)

On-Chip Protection of Cryptographic ICs Against Physical Side Channel Attacks: Invited Paper. - Makoto Nagata (ASICON, 2019)

A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar. - Noriyuki Miura; Tatsuya Machida; Kohei Matsuda; Makoto Nagata; Shoei Nashimoto; Daisuke Suzuki (ASHES@CCS, 2019)

On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper. - Makoto Nagata; Takuji Miki; Noriyuki Miura (CICC, 2019)

Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security - Invited Paper. - Makoto Nagata (SPACE, 2019)

A 0.72pJ/bit 400μm2 Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes. - Takuji Miki; Noriyuki Miura; Makoto Nagata (IEICE Trans. Electron., 2019)

Side-channel leakage from sensor-based countermeasures against fault injection attack. - Takeshi Sugawara 001; Natsu Shoji; Kazuo Sakiyama; Kohei Matsuda; Noriyuki Miura; Makoto Nagata (Microelectron. J., 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Fast and Comprehensive Simulation Methodology for Layout-Based Power-Noise Side-Channel Leakage Analysis. - Lang Lin; Dinesh Selvakumaran; Deqi Zhu; Norman Chang; Calvin Chow; Makoto Nagata; Kazuki Monta (iSES, 2020)

A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation. - Yoshihide Komatsu; Akinori Shinmyo; Mayuko Fujita; Tsuyoshi Hiraki; Kouichi Fukuda; Noriyuki Miura; Makoto Nagata (IEICE Trans. Electron., 2020)

Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. - Takuji Miki; Makoto Nagata; Hiroki Sonoda; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEEE J. Solid State Circuits, 2020)

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. - Rei Ueno; Naofumi Homma; Sumio Morioka; Noriyuki Miura; Kohei Matsuda; Makoto Nagata; Shivam Bhasin; Yves Mathieu; Tarik Graba; Jean-Luc Danger (IEEE Trans. Computers, 2020)

A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack. - Takuji Miki; Noriyuki Miura; Hiroki Sonoda; Kento Mizuta; Makoto Nagata (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring. - Kazuki Monta; Leonidas Katselas; Ferenc Fodor; Alkis A. Hatzopoulos; Makoto Nagata; Erik Jan Marinissen (ETS, 2021)

Multiphysics Simulation of EM Side-Channels from Silicon Backside with ML-based Auto-POI Identification. - Lang Lin; Deqi Zhu; Jimin Wen; Hua Chen; Yu Lu; Norman Chang; Calvin Chow; Harsh Shrivastav; Chia-Wei Chen; Kazuki Monta; Makoto Nagata (HOST, 2021)

Chip Stacking and Packaging Technology Explorations for Hardware Security (Invited). - Makoto Nagata (SLIP, 2021)

Landside capacitor efficacy among multi-chip-module using Si-interposer. - Yuuki Araga; Ryo Kasai; Daisuke Tanaka; Yoshihide Murakami; Kyoshi Mihara; Kazuo Makida; Hiroki Sonoda; Makoto Nagata; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEICE Electron. Express, 2021)

Foreword. - Makoto Nagata (IEICE Trans. Electron., 2021)

Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure. - Shoei Nashimoto; Daisuke Suzuki; Noriyuki Miura; Tatsuya Machida; Kohei Matsuda; Makoto Nagata (J. Cryptogr. Eng., 2021)

Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. - Ville Yli-Mäyry; Rei Ueno; Noriyuki Miura; Makoto Nagata; Shivam Bhasin; Yves Mathieu; Tarik Graba; Jean-Luc Danger; Naofumi Homma (IEEE Trans. Inf. Forensics Secur., 2021)

Exploring Fault Injection Attack Resilience of Secure IC Chips : Invited Paper. - Makoto Nagata (IRPS, 2022)

Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging. - Takuya Wadatsumi; Kohei Kawai; Rikuu Hasegawa; Takuji Miki; Makoto Nagata; Kikuo Muramatsu; Hiromu Hasegawa; Takuya Sawada; Takahito Fukushima; Hisashi Kondo (IRPS, 2022)

Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements. - Kazuki Monta; Leonidas Katselas; Ferenc Fodor; Takuji Miki; Alkis A. Hatzopoulos; Makoto Nagata; Erik Jan Marinissen (IEEE Des. Test, 2022)

An 11-bit 0.008mm2 charge-redistribution digital-to-analog converter operating at cryogenic temperature for large-scale qubit arrays. - Takuji Miki; Ryozo Takahashi; Makoto Nagata (IEICE Electron. Express, 2022)

Physical Attack Protection Techniques for IC Chip Level Hardware Security. - Makoto Nagata; Takuji Miki; Noriyuki Miura (IEEE Trans. Very Large Scale Integr. Syst., 2022)

On the Unpredictability of SPICE Simulations for Side-Channel Leakage Verification of Masked Cryptographic Circuits. - Kazuki Monta; Makoto Nagata; Josep Balasch; Ingrid Verbauwhede (DAC, 2023)

Characterization of Backside ESD Impacts on Integrated Circuits. - Takuya Wadatsumi; Kohei Kawai; Rikuu Hasegawa; Kazuki Monta; Takuji Miki; Makoto Nagata (IRPS, 2023)

A Triturated Sensing System. - Noriyuki Miura; Kotaro Naruse; Jun Shiomi; Yoshihiro Midoh; Tetsuya Hirose; Takaaki Okidono; Takuji Miki; Makoto Nagata (ISSCC, 2023)

Findings of the 2023 Conference on Machine Translation (WMT23): LLMs Are Here but Not Quite There Yet. - Tom Kocmi; Eleftherios Avramidis; Rachel Bawden; Ondrej Bojar; Anton Dvorkovich; Christian Federmann; Mark Fishel; Markus Freitag; Thamme Gowda; Roman Grundkiewicz; Barry Haddow; Philipp Koehn; et al. (WMT, 2023)

Guest Editorial IEEE 2022 European Solid-State Circuits Conference. - Makoto Nagata; Massimo Alioto (IEEE J. Solid State Circuits, 2023)

Silicon-correlated Simulation Methodology of EM Side-channel Leakage Analysis. - Kazuki Monta; Lang Lin; Jimin Wen; Harsh Shrivastav; Calvin Chow; Hua Chen; Joao Geada; Sreeja Chowdhury; Nitin Pundir; Norman Chang; Makoto Nagata (ACM J. Emerg. Technol. Comput. Syst., 2023)

Design of Circuits and Packaging Systems for Security Chips. - Makoto Nagata (IEICE Trans. Electron., 2023)

An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique. - Ryozo Takahashi; Takuji Miki; Makoto Nagata (IEICE Trans. Electron., 2023)

Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging. - Takuya Wadatsumi; Kohei Kawai; Rikuu Hasegawa; Kikuo Muramatsu; Hiromu Hasegawa; Takuya Sawada; Takahito Fukushima; Hisashi Kondo; Takuji Miki; Makoto Nagata (IEICE Trans. Electron., 2023)

Thermal Flow Simuation and Measurements of 3D Si Chip Stacks with TSVs. - Shuhei Yokota; Rikuu Hasegawa; Kazuki Monta; Takaaki Okidono; Takuji Miki; Makoto Nagata (3DIC, 2024)

A Hybrid Simulation Approach for Accurate and Fast System-Level Side-Channel Leakage Evaluation. - Kazuki Monta; Takafumi Oki; Rikuu Hasegawa; Takuya Wadatsumi; Takuji Miki; Makoto Nagata; Lang Lin; Norman Chang (AsianHOST, 2024)

A cryogenic pulse shaper for spin qubit control utilizing 1ns-time-resolution ADCs on an active silicon interposer operating at sub-100 mK temperatures. - Ryozo Takahashi; Yusuke Kanno; Takuji Miki; Nobuhiro Kusuno; Hiroyuki Mizuno; Makoto Nagata (A-SSCC, 2024)

On-Chip Evaluation of Voltage Drops and Fault Occurrence Induced by Si Backside EM Injection. - Rikuu Hasegawa; Kazuki Monta; Takuya Wadatsumi; Takuji Miki; Makoto Nagata (COSADE, 2024)

Accuracy of GPS Positioning Measurements in response to Electromagnetic Noise Characteristics. - Hiraku Uehara; Koh Watanabe; Sosuke Ashida; Yushi Mitsuya; Satoshi Tanaka; Makoto Nagata (EMC Compo, 2024)

Modeling and Analysis of On-Chip Voltage Fluctuations Caused by Electromagnetic Fault Injection. - Takuya Wadatsumi; Rikuu Hasegawa; Kazuki Monta; Takuji Miki; Lang Lin; Norman Chang; Makoto Nagata (EMC Compo, 2024)

Fault Injection Attacks Exploiting High Voltage Pulsing over Si-Substrate Backside of IC chips. - Yusuke Hayashi; Rikuu Hasegawa; Takuya Wadatsumi; Kazuki Monta; Takuji Miki; Makoto Nagata (FDTC, 2024)

Photon Emission Modeling and Machine-Learning Assisted Pre-Silicon Optical Side-Channel Simulation. - Henian Li; Lang Lin; Norman Chang; Sreeja Chowdhury; Dylan Mcguire; Bozidar Novakovic; Kazuki Monta; Makoto Nagata; Ying-Shiun Li; Pramod M. S; Piin-Chen Yeh; Jyh-Shing Roger Jang; et al. (HOST, 2024)

Si-Backside Side-Channel Leakage Measurement and Simulation. - Rikuu Hasegawa; Kazuki Monta; Takuya Wadatsumi; Takuji Miki; Makoto Nagata; Lang Lin; Akhilesh Kumar; Norman Chang (ISOCC, 2024)

Electromagnetic Interference With the Mobile Communication Devices in Unmanned Aerial Vehicles and Its Countermeasures. - Koh Watanabe; Ryota Sakai; Satoshi Tanaka; Makoto Nagata; Hideki Osaka; Atsushi Nakamura; Ifong Wu; Yasushi Matsumoto; Kaoru Gotoh (IEEE Access, 2024)

ML-EMFI: A Machine Learning-Driven Pre-Silicon Electromagnetic Fault Injection Security Evaluation for Robust IC Design. - Pantha Protim Sarker; Tianze Kan; Jingchen Liang; Ozgur Tuncer; Bo He; Zelin Lu; Sudarshan Mallu; Lang Lin; Norman Chang; Rikuu Hasegawa; Kazuki Monta; Makoto Nagata; et al. (HOST, 2025)