Transparent SOC: on-chip analyzing techniques and implementation for embedded processor. - Makoto Saen; Motohiro Nakagawa; Junichi Nishimoto; Tomoyuki Kodama; Fumio Arakawa (SoCC, 2004)

Elastic shared resource scheduling SOC interconnect architecture for real-time system. - Makoto Saen; Hiroshi Ueda; Masaru Hase; Eiji Yamamoto; Yoshihiro Mori; Hiroshi Hatae; Yuki Kondo; Seiji Miura; Itaru Nonomura; Naohiko Irie; Hiromi Watanabe (CICC, 2005)

Embedded SoC Resource Manager to Control Temperature and Data Bandwidth. - Makoto Saen; Kenichi Osada; Satoshi Misaka; Tetsuya Yamada; Yoshitaka Tsujimoto; Yuki Kondo; Tatsuya Kamei; Yutaka Yoshida; Ei Nagahama; Yusuke Nitta; Takayasu Ito; Tadashi Kameyama; et al. (ISSCC, 2007)

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. - Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Makoto Saen; Shigenobu Komatsu; Kenichi Osada; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (ISSCC, 2009)

Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration. - Kiyoto Ito; Makoto Saen; Kenichi Osada; Tomoyuki Kodama; Hiroyuki Mizuno (3DIC, 2010)

A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS. - Masafumi Onouchi; Yusuke Kanno; Makoto Saen; Shigenobu Komatsu; Yoshihiko Yasu; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2010)

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. - Makoto Saen; Kenichi Osada; Yasuyuki Okuma; Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (IEEE J. Solid State Circuits, 2010)

Scalable robotic-hand control system based on a hierarchical multi-processor architecture adopting a large number of tactile sensors. - Kiyoto Ito; Makoto Saen; Kenichi Osada (IROS, 2012)

Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA. - Makoto Saen; Tadanobu Toba; Yusuke Kanno (IEICE Trans. Electron., 2017)