A novel test methodology for core-based system LSIs and a testing time minimization problem. - Makoto Sugihara; Hiroshi Date; Hiroto Yasuura (ITC, 1998)

Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. - Makoto Sugihara; Hiroto Yasuura; Hiroshi Date (DATE, 2000)

Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores. - Hiroshi Date; Vikram Iyengar; Krishnendu Chakrabarty; Makoto Sugihara (PDPTA, 2000)

Optimization of Test Accesses with a Combined BIST and External Test Scheme. - Makoto Sugihara; Hiroto Yasuura (ASP-DAC/VLSI Design, 2002)

Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. - Makoto Sugihara; Kazuaki J. Murakami; Yusuke Matsunaga (ISVLSI, 2004)

Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. - Makoto Sugihara; Taiga Takata; Kenta Nakamura; Ryoichi Inanami; Hiroaki Hayashi; Katsumi Kishimoto; Tetsuya Hasebe; Yukihiro Kawano; Yusuke Matsunaga; Kazuaki J. Murakami; Katsuya Okumura (SoC, 2005)

A character size optimization technique for throughput enhancement of character projection lithography. - Makoto Sugihara; Taiga Takata; Kenta Nakamura; Ryoichi Inanami; Hiroaki Hayashi; Katsumi Kishimoto; Tetsuya Hasebe; Yukihiro Kawano; Yusuke Matsunaga; Kazuaki J. Murakami; Katsuya Okumura (ISCAS, 2006)

A Simulation-Based Soft Error Estimation Methodology for Computer Systems. - Makoto Sugihara; Tohru Ishihara; Masanori Muroyama; Koji Hashimoto (ISQED, 2006)

Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. - Makoto Sugihara; Taiga Takata; Kenta Nakamura; Ryoichi Inanami; Hiroaki Hayashi; Katsumi Kishimoto; Tetsuya Hasebe; Yukihiro Kawano; Yusuke Matsunaga; Kazuaki J. Murakami; Katsuya Okumura (IEICE Trans. Electron., 2006)

Task scheduling for reliable cache architectures of multiprocessor systems. - Makoto Sugihara; Tohru Ishihara; Kazuaki J. Murakami (DATE, 2007)

Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems. - Makoto Sugihara; Tohru Ishihara; Kazuaki J. Murakami (IEICE Trans. Electron., 2007)

Technology Mapping Technique for Increasing Throughput of Character Projection Lithography. - Makoto Sugihara; Kenta Nakamura; Yusuke Matsunaga; Kazuaki J. Murakami (IEICE Trans. Electron., 2007)

SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems. - Makoto Sugihara (ISQED, 2008)

Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems. - Makoto Sugihara; Tohru Ishihara; Kazuaki J. Murakami (IEICE Trans. Electron., 2008)

Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems. - Makoto Sugihara; Yusuke Matsunaga; Kazuaki J. Murakami (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints. - Makoto Sugihara (DSD, 2009)

Reliability Inherent in Heterogeneous Multiprocessor Systems and Task Scheduling for Ameliorating Their Reliability. - Makoto Sugihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Dynamic Control Flow Checking Technique for Reliable Microprocessors. - Makoto Sugihara (DSD, 2010)

Character-Size Optimization for Reducing the Number of EB Shots of MCC Lithographic Systems. - Makoto Sugihara (IEICE Trans. Electron., 2010)

On Synthesizing a Reliable Multiprocessor for Embedded Systems. - Makoto Sugihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Dynamic Continuous Signature Monitoring Technique for Reliable Microprocessors. - Makoto Sugihara (IEICE Trans. Electron., 2011)

Minimization of FlexRay Bus Bandwidth for Hard Real-Time Applications. - Makoto Sugihara; Akihito Iwanaga (J. Inf. Process., 2013)

Slot Multiplexing Optimization for Minimizing the Operating Frequency of a FlexRay Bus under Hard Real-time Constraints. - Makoto Sugihara; Akihito Iwanaga (J. Inf. Process., 2013)

Minimization of the Fabrication Cost for a Bridged-Bus-Based TDMA System under Hard Real-Time Constraints. - Makoto Sugihara (IEICE Trans. Inf. Syst., 2014)