A 45-ns 64-Mb DRAM with a merged match-line test architecture. - Shigeru Mori; Hiroshi Miyamoto; Yoshikazu Morooka; Shigeru Kikuda; Makoto Suwa; Mitsuya Kinoshita; Atsushi Hachisuka; Hideaki Arima; Michihiro Yamada; Tsutomu Yoshihara; Shimpei Kayano (IEEE J. Solid State Circuits, 1991)

An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM. - Kiyohiro Furutani; Hiroshi Miyamoto; Yoshikazu Morooka; Makoto Suwa; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1994)