A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. - Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; et al. (ISSCC, 2007)

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. - Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (ISSCC, 2007)

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. - Shigeki Ohbayashi; Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Susumu Imaoka; Yuji Oda; Tsutomu Yoshihara; Motoshige Igarashi; Masahiko Takeuchi; Hiroshi Kawashima; Yasuo Yamaguchi; Kazuhiro Tsukamoto; et al. (IEEE J. Solid State Circuits, 2007)

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. - Satoshi Ishikura; Marefusa Kurumada; Toshio Terano; Yoshinobu Yamagami; Naoki Kotani; Katsuji Satomi; Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Toshiyuki Oashi; Hiroshi Makino; et al. (IEEE J. Solid State Circuits, 2008)

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. - Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (IEEE J. Solid State Circuits, 2008)

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. - Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; et al. (IEEE J. Solid State Circuits, 2008)

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. - Koji Nii; Yasumasa Tsukamoto; Makoto Yabuuchi; Yasuhiro Masuda; Susumu Imaoka; Keiichi Usui; Shigeki Ohbayashi; Hiroshi Makino; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2009)

A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias. - Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Yuuichi Hirano; Toshiaki Iwamatsu; Yuji Kihara (ISSCC, 2010)

Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. - Koji Nii; Makoto Yabuuchi; Hidehiro Fujiwara; Hirofumi Nakano; Kazuya Ishihara; Hiroyuki Kawai; Kazutami Arimoto (SoCC, 2010)

A dynamic body-biased SRAM with asymmetric halo implant MOSFETs. - Makoto Yabuuchi; Yasumasa Tsukamoto; Hidehiro Fujiwara; Shigeki Tawa; Koji Maekawa; Motoshige Igarashi; Koji Nii (ISLPED, 2011)

A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. - Koji Nii; Yasumasa Tsukamoto; Yuichiro Ishii; Makoto Yabuuchi; Hidehiro Fujiwara; Kazuyoshi Okamoto (Asian Test Symposium, 2012)

Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application. - Yasumasa Tsukamoto; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Changhwan Shin; Tsu-Jae King Liu (ISQED, 2012)

A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. - Yuichiro Ishii; Yasumasa Tsukamoto; Koji Nii; Hidehiro Fujiwara; Makoto Yabuuchi; Koji Tanaka; Shinji Tanaka; Yasuhisa Shimazaki (ISSCC, 2012)

A stable chip-ID generating physical uncloneable function using random address errors in SRAM. - Hidehiro Fujiwara; Makoto Yabuuchi; Yasumasa Tsukamoto; Hirofumi Nakano; Toru Owada; Hiroyuki Kawai; Koji Nii (SoCC, 2012)

A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure. - Makoto Yabuuchi; Hidehiro Fujiwara; Yasumasa Tsukamoto; Miki Tanaka; Shinji Tanaka; Koji Nii (CICC, 2013)

A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. - Koji Nii; Makoto Yabuuchi; Hidehiro Fujiwara; Yasumasa Tsukamoto; Yuichiro Ishii; Tetsuya Matsumura; Yoshio Matsuda (ISQED, 2013)

Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS. - Hidehiro Fujiwara; Makoto Yabuuchi; Koji Nii (ISQED, 2014)

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. - Yohei Nakata; Yuta Kimi; Shunsuke Okumura; Jinwook Jung; Takuya Sawada; Taku Toshikawa; Makoto Nagata; Hirofumi Nakano; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Hiroyuki Kawai; et al. (ISQED, 2014)

13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists. - Makoto Yabuuchi; Yasumasa Tsukamoto; Masao Morimoto; Miki Tanaka; Koji Nii (ISSCC, 2014)

A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. - Shinji Tanaka; Yuichiro Ishii; Makoto Yabuuchi; Toshiaki Sano; Koji Tanaka; Yasumasa Tsukamoto; Koji Nii; Hirotoshi Sato (VLSIC, 2014)

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. - Yohei Nakata; Yuta Kimi; Shunsuke Okumura; Jinwook Jung; Takuya Sawada; Taku Toshikawa; Makoto Nagata; Hirofumi Nakano; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Hiroyuki Kawai; et al. (IEICE Trans. Electron., 2014)

28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. - Yukiko Umemoto; Koji Nii; Jiro Ishikawa; Makoto Yabuuchi; Kazuyoshi Okamoto; Yasumasa Tsukamoto; Shinji Tanaka; Koji Tanaka; Tetsuya Matsumura; Kazutaka Mori; Kazumasa Yanagisawa (IEEE Trans. Very Large Scale Integr. Syst., 2014)

1.8 Mbit/mm2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology. - Yasumasa Tsukamoto; Masao Morimoto; Makoto Yabuuchi; Miki Tanaka; Koji Nii (VLSIC, 2015)

A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry. - Yuichiro Ishii; Makoto Yabuuchi; Yohei Sawada; Masao Morimoto; Yasumasa Tsukamoto; Yuta Yoshida; Ken Shibata; Toshiaki Sano; Shinji Tanaka; Koji Nii (A-SSCC, 2016)

A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time. - Makoto Yabuuchi; Yohei Sawada; Toshiaki Sano; Yuichiro Ishii; Shinji Tanaka; Miki Tanaka; Koji Nii (VLSI Circuits, 2016)

40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications. - Yoshisato Yokoyama; Tomohiro Miura; Yukari Ouchi; Daisuke Nakamura; Jiro Ishikawa; Shunya Nagata; Makoto Yabuuchi; Yuichiro Ishii; Koji Nii (A-SSCC, 2018)

12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM. - Makoto Yabuuchi; Masao Morimoto; Koji Nii; Shinji Tanaka (VLSI Circuits, 2018)

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures. - Makoto Yabuuchi; Yasumasa Tsukamoto; Hidehiro Fujiwara; Miki Tanaka; Shinji Tanaka; Koji Nii (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process. - Mitsuhiko Igarashi; Yuuki Uchida; Yoshio Takazawa; Makoto Yabuuchi; Yasumasa Tsukamoto; Koji Shibutani (IRPS, 2019)

A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2. - Shunsuke Okumura; Makoto Yabuuchi; Kenichiro Hijioka; Koichi Nose (VLSI Circuits, 2019)

A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier. - Makoto Yabuuchi; Masao Morimoto; Yasumasa Tsukamoto; Shinji Tanaka (VLSI Circuits, 2020)

A 29.2 Mb/mm2 Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit. - Yoshisato Yokoyama; Miki Tanaka; Koji Tanaka; Masao Morimoto; Makoto Yabuuchi; Yuichiro Ishii; Shinji Tanaka (VLSI Circuits, 2020)

An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM. - Mitsuhiko Igarashi; Yuuki Uchida; Yoshio Takazawa; Makoto Yabuuchi; Yasumasa Tsukamoto; Koji Shibutani; Kazutoshi Kobayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. - Yumito Aoyagi; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Koji Nii; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction. - Tomotaka Tanaka; Yuichiro Ishii; Makoto Yabuuchi; Yumito Aoyagi; Masaya Hamada; Kazuto Mizutani; Koji Nii; Hidehiro Fujiwara; Isabel Wang; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2024)

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking. - Yumito Aoyagi; Koji Nii; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2024)