Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. - Gert Jervan; Petru Eles; Zebo Peng; Raimund Ubar; Maksim Jenihhin (DFT, 2003)

Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting. - Raimund Ubar; Maksim Jenihhin (DELTA, 2004)

Test Time Minimization for Hybrid BIST of Core-Based Systems. - Gert Jervan; Petru Eles; Zebo Peng; Raimund Ubar; Maksim Jenihhin (J. Comput. Sci. Technol., 2006)

Layout to Logic Defect Analysis for Hierarchical Test Generation. - Maksim Jenihhin; Jaan Raik; Raimund Ubar; Witold A. Pleskacz; Michal Rakowski (DDECS, 2007)

Code Coverage Analysis using High-Level Decision Diagrams. - Jaan Raik; Uljana Reinsalu; Raimund Ubar; Maksim Jenihhin; Peeter Ellervee (DDECS, 2008)

Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. - Raimund Ubar; Sergei Devadze; Maksim Jenihhin; Jaan Raik; Gert Jervan; Peeter Ellervee (DELTA, 2008)

Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. - Witold A. Pleskacz; Maksim Jenihhin; Jaan Raik; Michal Rakowski; Raimund Ubar; Wieslaw Kuzmicz (DSD, 2008)

Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. - Maksim Jenihhin; Jaan Raik; Anton Chepurov; Raimund Ubar (ETS, 2008)

Mixed hierarchical-functional fault models for targeting sequential cores. - Jaan Raik; Raimund Ubar; Taavi Viilukas; Maksim Jenihhin (J. Syst. Archit., 2008)

High-Level Decision Diagrams based coverage metrics for verification and test. - Maksim Jenihhin; Jaan Raik; Anton Chepurov; Uljana Reinsalu; Raimund Ubar (LATW, 2009)

PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams. - Maksim Jenihhin; Jaan Raik; Anton Chepurov; Raimund Ubar (J. Electron. Test., 2009)

Constraint-based test pattern generation at the Register-Transfer Level. - Taavi Viilukas; Jaan Raik; Maksim Jenihhin; Raimund Ubar; Anna Krivenko (DDECS, 2010)

An approach for PSL assertion coverage analysis with high-level decision diagrams. - Maksim Jenihhin; Jaan Raik; Raimund Ubar; Tatjana Shchenova (EWDTS, 2010)

Mutation analysis with high-level decision diagrams. - Hanno Hantson; Jaan Raik; Maksim Jenihhin; Anton Chepurov; Raimund Ubar; Giuseppe Di Guglielmo; Franco Fummi (LATW, 2010)

Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. - Jaan Raik; Anna Rannaste; Maksim Jenihhin; Taavi Viilukas; Raimund Ubar; Hideo Fujiwara (ETS, 2011)

Automated test bench generation for high-level synthesis flow ABELITE. - Taavi Viilukas; Maksim Jenihhin; Jaan Raik; Raimund Ubar; Samary Baranov (EWDTS, 2011)

EEG Analyzer prototype based on FPGA. - Maksim Jenihhin; Maksim Gorev; Vadim Pesonen; Dmitri Mihhailov; Peeter Ellervee; Hiie Hinrikus; Maie Bachmann; Jaanus Lass (ISPA, 2011)

Mutation analysis for SystemC designs at TLM. - Valerio Guarnieri; Nicola Bombieri; Graziano Pravadelli; Franco Fummi; Hanno Hantson; Jaan Raik; Maksim Jenihhin; Raimund Ubar (LATW, 2011)

Combining dynamic slicing and mutation operators for ESL correction. - Urmas Repinski; Hanno Hantson; Maksim Jenihhin; Jaan Raik; Raimund Ubar; Giuseppe Di Guglielmo; Graziano Pravadelli; Franco Fummi (ETS, 2012)

Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis. - Hanno Hantson; Urmas Repinski; Jaan Raik; Maksim Jenihhin; Raimund Ubar (LATW, 2012)

PSL assertion checkers synthesis with ASM based HLS tool ABELITE. - Maksim Jenihhin; Samary Baranov; Jaan Raik; Valentin Tihhomirov (LATW, 2012)

Localization of Bugs in Processor Designs Using zamiaCAD Framework. - Anton Tsepurov; Valentin Tihhomirov; Maksim Jenihhin; Jaan Raik; Gunter Bartsch; Jorge Hernán Meza Escobar; Heinz-Dietrich Wuttke (MTV, 2012)

A scalable model based RTL framework zamiaCAD for static analysis. - Anton Tsepurov; Gunter Bartsch; Rainer Dorsch; Maksim Jenihhin; Jaan Raik; Valentin Tihhomirov (VLSI-SoC, 2012)

On the Reuse of TLM Mutation Analysis at RTL. - Valerio Guarnieri; Giuseppe Di Guglielmo; Nicola Bombieri; Graziano Pravadelli; Franco Fummi; Hanno Hantson; Jaan Raik; Maksim Jenihhin; Raimund Ubar (J. Electron. Test., 2012)

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. - Taavi Viilukas; Anton Karputkin; Jaan Raik; Maksim Jenihhin; Raimund Ubar; Hideo Fujiwara (J. Electron. Test., 2012)

Extensible open-source framework for translating RTL VHDL IP cores to SystemC. - Syed Saif Abrar; Maksim Jenihhin; Jaan Raik (DDECS, 2013)

Identifying NBTI-Critical Paths in Nanoscale Logic. - Raimund Ubar; Fabian Vargas 001; Maksim Jenihhin; Jaan Raik; Sergei Kostin; Letícia Maria Bolzani Poehls (DSD, 2013)

Performance analysis of cosimulating processor core in VHDL and SystemC. - Syed Saif Abrar; Maksim Jenihhin; Jaan Raik; Shyam Kiran A.; C. Babu (ICACCI, 2013)

Assessment of diagnostic test for automated bug localization. - Valentin Tihhomirov; Anton Tsepurov; Maksim Jenihhin; Jaan Raik; Raimund Ubar (LATW, 2013)

Automated design error debug using high-level decision diagrams and mutation operators. - Jaan Raik; Urmas Repinski; Anton Chepurov; Hanno Hantson; Raimund Ubar; Maksim Jenihhin (Microprocess. Microsystems, 2013)

Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation. - Marco Gaudesi; Maksim Jenihhin; Jaan Raik; Ernesto Sánchez 001; Giovanni Squillero; Valentin Tihhomirov; Raimund Ubar (EvoApplications, 2014)

Hierarchical identification of NBTI-critical gates in nanoscale logic. - Sergei Kostin; Jaan Raik; Raimund Ubar; Maksim Jenihhin; Fabian Vargas 001; Letícia Maria Bolzani Poehls; Thiago Santos Copetti (LATW, 2014)

Automated Design Error Localization in RTL Designs. - Maksim Jenihhin; Anton Tsepurov; Valentin Tihhomirov; Jaan Raik; Hanno Hantson; Raimund Ubar; Gunter Bartsch; Jorge Hernán Meza Escobar; Heinz-Dietrich Wuttke (IEEE Des. Test, 2014)

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores. - Syed Saif Abrar; Maksim Jenihhin; Jaan Raik (DDECS, 2015)

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. - Sergei Kostin; Jaan Raik; Raimund Ubar; Maksim Jenihhin; Thiago Copetti; Fabian Vargas 001; Letícia Maria Bolzani Pöhls (DDECS, 2015)

FSMD RTL design manipulation for clock interface abstraction. - Syed Saif Abrar; Maksim Jenihhin; Jaan Raik (ICACCI, 2015)

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG. - N. Palermo; Valentin Tihhomirov; Thiago Santos Copetti; Maksim Jenihhin; Jaan Raik; Sergei Kostin; Marco Gaudesi; Giovanni Squillero; Matteo Sonza Reorda; Fabian Vargas 001; Letícia Maria Bolzani Pöhls (LATS, 2015)

Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. - Francesco Pellerey; Maksim Jenihhin; Giovanni Squillero; Jaan Raik; Matteo Sonza Reorda; Valentin Tihhomirov; Raimund Ubar (ATS, 2016)

Universal mitigation of NBTI-induced aging by design randomization. - Maksim Jenihhin; Alexander Kamkin; Zainalabedin Navabi; Somayeh Sadeghi Kohan (EWDTS, 2016)

Designing reliable cyber-physical systems overview associated to the special session at FDL'16. - Gadi Aleksandrowicz; Eli Arbel; Roderick Bloem; Timon D. ter Braak; Sergei Devadze; Görschwin Fey; Maksim Jenihhin; Artur Jutman; Hans G. Kerkhoff; Robert Könighofer; Jan Malburg; Shiri Moran; et al. (FDL, 2016)

Gate-level modelling of NBTI-induced delays under process variations. - Thiago Copetti; Guilherme Medeiros Machado; Leticia Bolzani Poehls; Fabian Vargas 001; Sergei Kostin; Maksim Jenihhin; Jaan Raik; Raimund Ubar (LATS, 2016)

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. - Maksim Jenihhin; Giovanni Squillero; Thiago Santos Copetti; Valentin Tihhomirov; Sergei Kostin; Marco Gaudesi; Fabian Vargas 001; Jaan Raik; Matteo Sonza Reorda; Leticia Bolzani Poehls; Raimund Ubar; Guilherme Cardoso Medeiros (J. Electron. Test., 2016)

BASTION: Board and SoC test instrumentation for ageing and no failure found. - Artur Jutman; Christophe Lotz; Erik Larsson; Matteo Sonza Reorda; Maksim Jenihhin; Jaan Raik; Hans G. Kerkhoff; Rene Krenz-Baath; Piet Engelke (DATE, 2017)

A scalable technique to identify true critical paths in sequential circuits. - Raimund Ubar; Sergei Kostin; Maksim Jenihhin; Jaan Raik (DDECS, 2017)

Multi-Fragment Markov Model Guided Online Test Generation for MPSoC. - Jüri Vain; Leonidas Tsiopoulos; Vyacheslav S. Kharchenko; Apneet Kaur; Maksim Jenihhin; Jaan Raik (ICTERI, 2017)

QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications. - Serhiy Avramenko; Siavoosh Payandeh Azad; Stefano Esposito; Behrad Niazmand; Massimo Violante; Jaan Raik; Maksim Jenihhin (DDECS, 2018)

Software-Level TMR Approach for On-Board Data Processing in Space Applications. - Karl Janson; Carl Johann Treudler; Thomas Hollstein; Jaan Raik; Maksim Jenihhin; Görschwin Fey (DDECS, 2018)

RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality. - Heinrich Theodor Vierhaus; Maksim Jenihhin; Matteo Sonza Reorda (EWME, 2018)

Timing-critical path analysis with structurally synthesized BDDs. - Raimund Ubar; Lembit Jurimagi; Maksim Jenihhin; Jaan Raik; Niyi-Leigh Olugbenga; Vladimir Viies (MECO, 2018)

Towards Multidimensional Verification: Where Functional Meets Non-Functional. - Maksim Jenihhin; Xinhui Lai; Tara Ghasempouri; Jaan Raik (NORCAS, 2018)

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. - Lembit Jurimagi; Raimund Ubar; Maksim Jenihhin; Jaan Raik; Sergei Devadze; Sergei Kostin (PATMOS, 2018)

Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis. - Serhiy Avramenko; Siavoosh Payandeh Azad; Behrad Niazmand; Massimo Violante; Jaan Raik; Maksim Jenihhin (VLSI-SoC, 2018)

Fast identification of true critical paths in sequential circuits. - Raimund Ubar; Sergei Kostin; Maksim Jenihhin; Jaan Raik; Lembit Jürimägi (Microelectron. Reliab., 2018)

Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. - Aneesh Balakrishnan; Thomas Lange; Maximilien Glorieux; Dan Alexandrescu; Maksim Jenihhin (AHS, 2019)

New categories of Safe Faults in a processor-based Embedded System. - Cemil Cem Gürsoy; Maksim Jenihhin; Adeboye Stephen Oyeniran; Davide Piumatti; Jaan Raik; Matteo Sonza Reorda; Raimund Ubar (DDECS, 2019)

Challenges of Reliability Assessment and Enhancement in Autonomous Systems. - Maksim Jenihhin; Matteo Sonza Reorda; Aneesh Balakrishnan; Dan Alexandrescu (DFT, 2019)

True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits. - Raimund Ubar; Lembit Jürimägi; Adeniyi Olanrewaju Adekoya; Maksim Jenihhin (DSD, 2019)

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Cemil Cem Gürsoy; Jaan Raik (ETS, 2019)

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. - Saba Yousefzadeh; Katayoon Basharkhah; Nooshin Nosrati; Rezgar Sadeghi; Jaan Raik; Maksim Jenihhin; Zainalabedin Navabi (EWDTS, 2019)

Efficient Fault Injection based on Dynamic HDL Slicing Technique. - Ahmet Cagri Bagbaba; Maksim Jenihhin; Jaan Raik; Christian Sauer 001 (IOLTS, 2019)

Application Specific True Critical Paths Identification in Sequential Circuits. - Lembit Jürimägi; Raimund Ubar; Maksim Jenihhin; Jaan Raik; Sergei Devadze; Adeboye Stephen Oyeniran (IOLTS, 2019)

PASCAL: Timing SCA Resistant Design and Verification Flow. - Xinhui Lai; Maksim Jenihhin; Jaan Raik; Kolin Paul (IOLTS, 2019)

Software-Based Mitigation for Memory Address Decoder Aging. - Daniel H. P. Kraak; Cemil Cem Gürsoy; Innocent O. Agbo; Mottaqiallah Taouil; Maksim Jenihhin; Jaan Raik; Said Hamdioui (LATS, 2019)

Mixed-level identification of fault redundancy in microprocessors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Cemil Cem Gürsoy; Jaan Raik (LATS, 2019)

Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing. - Ahmet Cagri Bagbaba; Maksim Jenihhin; Jaan Raik; Christian Sauer 001 (NORCAS, 2019)

The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. - Aneesh Balakrishnan; Thomas Lange; Maximilien Glorieux; Dan Alexandrescu; Maksim Jenihhin (NORCAS, 2019)

On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks. - Aleksa Damljanovic; Giovanni Squillero; Cemil Cem Gürsoy; Maksim Jenihhin (VLSI-SoC, 2019)

Implementation-Independent Functional Test Generation for MSC Microprocessors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (VLSI-SoC, 2019)

On Test Generation for Microprocessors for Extended Class of Functional Faults. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (VLSI-SoC (Selected Papers), 2019)

An optimization framework for dynamic pipeline management in computing systems. - Syed Rameez Naqvi; Anjum Zahid; Lina Sawalha; Syed Saud Naqvi; Tallha Akram; Sajjad Ali Haider; Kumar Yelamarthi; Maksim Jenihhin (Comput. Electr. Eng., 2019)

High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Cemil Cem Gürsoy; Jaan Raik (CoRR, 2019)

Understanding multidimensional verification: Where functional meets non-functional. - Xinhui Lai; Aneesh Balakrishnan; Thomas Lange; Maksim Jenihhin; Tara Ghasempouri; Jaan Raik; Dan Alexandrescu (Microprocess. Microsystems, 2019)

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. - Maksim Jenihhin; Said Hamdioui; Matteo Sonza Reorda; Milos Krstic; Peter Langendörfer; Christian Sauer 001; Anton Klotz; Michael Hübner 001; Jörg Nolte; Heinrich Theodor Vierhaus; Georgios N. Selimis; Dan Alexandrescu; et al. (DATE, 2020)

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs. - Guilherme Cardoso Medeiros; Cemil Cem Gürsoy; Lizhou Wu; Moritz Fieback; Maksim Jenihhin; Mottaqiallah Taouil; Said Hamdioui (DATE, 2020)

Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (DSD, 2020)

Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. - Ahmet Cagri Bagbaba; Maksim Jenihhin; Raimund Ubar; Christian Sauer 001 (IOLTS, 2020)

Wafer-Level Die Re-Test Success Prediction Using Machine Learning. - Hardi Selg; Maksim Jenihhin; Peeter Ellervee (LATS, 2020)

Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects. - Aneesh Balakrishnan; Thomas Lange; Maximilien Glorieux; Dan Alexandrescu; Maksim Jenihhin (MECO, 2020)

Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. - Xinhui Lai; Maksim Jenihhin; Georgios N. Selimis; Sven Goossens; Roel Maes; Kolin Paul (VLSI-SOC, 2020)

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks. - Felipe Augusto da Silva; Ahmet Cagri Bagbaba; Annachiara Ruospo; Riccardo Mariani; Ghani Kanawati; Ernesto Sánchez 001; Matteo Sonza Reorda; Maksim Jenihhin; Said Hamdioui; Christian Sauer 001 (VTS, 2020)

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (J. Electron. Test., 2020)

Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs. - Lembit Jürimägi; Raimund Ubar; Maksim Jenihhin; Jaan Raik (Microprocess. Microsystems, 2020)

Modeling Soft-Error Reliability Under Variability. - Aneesh Balakrishnan; Guilherme Cardoso Medeiros; Cemil Cem Gürsoy; Said Hamdioui; Maksim Jenihhin; Dan Alexandrescu (DFT, 2021)

JÄNES: A NAS Framework for ML-based EDA Applications. - Hardi Selg; Maksim Jenihhin; Peeter Ellervee (DFT, 2021)

Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. - Maksim Jenihhin; Adeboye Stephen Oyeniran; Jaan Raik; Raimund Ubar (DSD, 2021)

Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis. - Aneesh Balakrishnan; Dan Alexandrescu; Maksim Jenihhin; Thomas Lange; Maximilien Glorieux (ISQED, 2021)

Edge-to-Fog Collaborative Computing in a Swarm of Drones. - Dadmehr Rahbari; Muhammad Mahtab Alam; Yannick Le Moullec; Maksim Jenihhin (MEDI Workshops, 2021)

A Methodology for Automated Mining of Compact and Accurate Assertion Sets. - Mohammad Reza Heidari Iman; Jaan Raik; Maksim Jenihhin; Gert Jervan; Tara Ghasempouri (NorCAS, 2021)

On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines. - Xinhui Lai; Thomas Lange; Aneesh Balakrishnan; Dan Alexandrescu; Maksim Jenihhin (VLSI-SoC, 2021)

Fast and Fair Computation Offloading Management in a Swarm of Drones Using a Rating-Based Federated Learning Approach. - Dadmehr Rahbari; Muhammad Mahtab Alam; Yannick Le Moullec; Maksim Jenihhin (IEEE Access, 2021)

MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors. - Nooshin Nosrati; Maksim Jenihhin; Zainalabedin Navabi (IOLTS, 2022)

A Novel Fault-Tolerant Logic Style with Self-Checking Capability. - Mahdi Taheri; Saeideh Sheikhpour; Ali Mahani 001; Maksim Jenihhin (IOLTS, 2022)

High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. - Adeboye Stephen Oyeniran; Maksim Jenihhin; Jaan Raik; Raimund Ubar (ISVLSI, 2022)

On BTI Aging Rejuvenation in Memory Address Decoders. - Cemil Cem Gürsoy; Daniel Kraak; Foisal Ahmed; Mottaqiallah Taouil; Maksim Jenihhin; Said Hamdioui (LATS, 2022)

A Survey on UAV Computing Platforms: A Hardware Reliability Perspective. - Foisal Ahmed; Maksim Jenihhin (Sensors, 2022)

Enhancing Fault Resilience of QNNs by Selective Neuron Splitting. - Mohammad Hasan Ahmadilivani; Mahdi Taheri; Jaan Raik; Masoud Daneshtalab; Maksim Jenihhin (AICAS, 2023)

APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors. - Mahdi Taheri; Mohammad Hasan Ahmadilivani; Maksim Jenihhin; Masoud Daneshtalab; Jaan Raik (DDECS, 2023)

On-Chip Sensors Data Collection and Analysis for SoC Health Management. - Konstantin Shibin; Maksim Jenihhin; Artur Jutman; Sergei Devadze; Anton Tsertov (DFT, 2023)

DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs' Reliability Assessment. - Mohammad Hasan Ahmadilivani; Mahdi Taheri; Jaan Raik; Masoud Daneshtalab; Maksim Jenihhin (ETS, 2023)

ML-Based Online Design Error Localization for RISC-V Implementations. - Hardi Selg; Maksim Jenihhin; Peeter Ellervee; Jaan Raik (IOLTS, 2023)

DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators. - Mahdi Taheri; Mohammad Riazati; Mohammad Hasan Ahmadilivani; Maksim Jenihhin; Masoud Daneshtalab; Jaan Raik; Mikael Sjödin; Björn Lisper (ISQED, 2023)

Holistic IJTAG-based External and Internal Fault Monitoring in UAVs. - Foisal Ahmed; Maksim Jenihhin (LATS, 2023)

Analyzing Side-Channel Attack Vulnerabilities at RTL. - Xinhui Lai; Maksim Jenihhin (LATS, 2023)

Special Session: Approximation and Fault Resiliency of DNN Accelerators. - Mohammad Hasan Ahmadilivani; Mario Barbareschi; Salvatore Barone; Alberto Bosio; Masoud Daneshtalab; Salvatore Della Torca; Gabriele Gavarini; Maksim Jenihhin; Jaan Raik; Annachiara Ruospo; Ernesto Sánchez 001; Mahdi Taheri (VTS, 2023)

Applying RIS-Based Communication for Collaborative Computing in a Swarm of Drones. - Dadmehr Rahbari; Muhammad Mahtab Alam; Yannick Le Moullec; Maksim Jenihhin (IEEE Access, 2023)

Unsupervised Recycled FPGA Detection Using Symmetry Analysis. - Tanvir Ahmad Tarique; Foisal Ahmed; Maksim Jenihhin; Liakot Ali (CoRR, 2023)

An automated method for mining high-quality assertion sets. - Mohammad Reza Heidari Iman; Jaan Raik; Maksim Jenihhin; Gert Jervan; Tara Ghasempouri (Microprocess. Microsystems, 2023)

Structural Decision Diagrams in Digital Test - Theory and Applications - Raimund Ubar; Jaan Raik; Maksim Jenihhin; Artur Jutman (Springer, 2024)

FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs. - Samira Nazari; Mahdi Taheri; Ali Azarpeyvand; Mohsen Afsharchi; Tara Ghasempouri; Christian Herglotz; Masoud Daneshtalab; Maksim Jenihhin (ATS, 2024)

SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. - Mahdi Taheri; Masoud Daneshtalab; Jaan Raik; Maksim Jenihhin; Salvatore Pappalardo; Paul Jiménez; Bastien Deveautour; Alberto Bosio (DDECS, 2024)

Special Session: In-Field ML-Assisted Intermittent Fault Localization and Management in RISC-V SoCs. - Hardi Selg; Konstantin Shibin; Anton Tsertov; Maksim Jenihhin; Peeter Ellervee; Jaan Raik (DFT, 2024)

IJTAG-compatible Symptom-based SEU Monitors for FPGA DNN Accelerators. - Natalia Cherezova; Maksim Jenihhin; Artur Jutman (DTTIS, 2024)

AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators. - Mahdi Taheri; Natalia Cherezova; Samira Nazari; Ahsan Rafiq; Ali Azarpeyvand; Tara Ghasempouri; Masoud Daneshtalab; Jaan Raik; Maksim Jenihhin (ETS, 2024)

Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning. - Mohammad Hasan Ahmadilivani; Seyedhamidreza Mousavi; Jaan Raik; Masoud Daneshtalab; Maksim Jenihhin (IOLTS, 2024)

Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators. - Mahdi Taheri; Natalia Cherezova; Mohammad Saeed Ansari; Maksim Jenihhin; Ali Mahani 001; Masoud Daneshtalab; Jaan Raik (ISQED, 2024)

Keynote: Cost-Efficient Reliability for Edge-AI Chips. - Maksim Jenihhin; Mahdi Taheri; Natalia Cherezova; Mohammad Hasan Ahmadilivani; Hardi Selg; Artur Jutman; Konstantin Shibin; Anton Tsertov; Sergei Devadze; Rama Mounika Kodamanchili; Ahsan Rafiq; Jaan Raik; et al. (LATS, 2024)

Heterogeneous Approximation of DNN HW Accelerators based on Channels Vulnerability. - Natalia Cherezova; Salvatore Pappalardo; Mahdi Taheri; Mohammad Hasan Ahmadilivani; Bastien Deveautour; Alberto Bosio; Jaan Raik; Maksim Jenihhin (VLSI-SoC, 2024)

Special Session: Reliability Assessment Recipes for DNN Accelerators. - Mohammad Hasan Ahmadilivani; Alberto Bosio; Bastien Deveautour; Fernando Fernandes dos Santos; Juan-David Guerrero-Balaguera; Maksim Jenihhin; Angeliki Kritikakou; Robert Limas Sierra; Salvatore Pappalardo; Jaan Raik; Josie E. Rodriguez Condia; Matteo Sonza Reorda; et al. (VTS, 2024)

ProAct: Progressive Training for Hybrid Clipped Activation Function to Enhance Resilience of DNNs. - Seyedhamidreza Mousavi; Mohammad Hasan Ahmadilivani; Jaan Raik; Maksim Jenihhin; Masoud Daneshtalab (CoRR, 2024)

DeepVigor+: Scalable and Accurate Semi-Analytical Fault Resilience Analysis for Deep Neural Network. - Mohammad Hasan Ahmadilivani; Jaan Raik; Masoud Daneshtalab; Maksim Jenihhin (CoRR, 2024)

A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks. - Mohammad Hasan Ahmadilivani; Mahdi Taheri; Jaan Raik; Masoud Daneshtalab; Maksim Jenihhin (ACM Comput. Surv., 2024)

Reliability-Critical Computation Offloading in UAV Swarms. - Dadmehr Rahbari; Foisal Ahmed; Maksim Jenihhin; Muhammad Mahtab Alam; Yannick Le Moullec (IEEE Syst. J., 2024)

RL-Agent-based Early-Exit DNN Architecture Search Framework. - Mahdi Taheri; Parth Patne; Natalia Cherezova; Ali Mahani 001; Christian Herglotz; Maksim Jenihhin (DDECS, 2025)

XMULT: An Energy-Efficient Design of Approximate Multiplier. - Ahsan Rafiq; Maksim Jenihhin (DSN-W, 2025)

European Test Symposium Teams: an Anniversary Snapshot. - Maksim Jenihhin; Jaan Raik; Artur Jutman; Natalia Cherezova; Raimund Ubar; Liviu Miclea; Szilárd Enyedi; I. Stefan; Ovidiu Stan; Cosmina Corches; Z. Peng; Petru Eles; et al. (ETS, 2025)

SHIELD: PSO-Based Hardware Trojan Detection for Efficient and Low-Cost Defense. - Mostafa Hosseini; Ali Azarpeyvand; Mahdi Taheri; Tara Ghasempouri; Maksim Jenihhin (IOLTS, 2025)

AxEnMULT: Design of an Efficient and Reliable Approximate Encoding-Based Multiplier. - Ahsan Rafiq; Alberto Bosio; Salvatore Pappalardo; Maksim Jenihhin (ISVLSI, 2025)

Reliability-Aware Performance Optimization of DNN HW Accelerators Through Heterogeneous Quantization. - Samira Nazari; Mahdi Taheri; Ali Azarpeyvand; Mohsen Afsharchi; Christian Herglotz; Maksim Jenihhin (LATS, 2025)

An Efficient Architecture for Edge AI Federated Learning With Homomorphic Encryption. - Dadmehr Rahbari; Masoud Daneshtalab; Maksim Jenihhin (IEEE Access, 2025)

FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inference. - Natalia Cherezova; Artur Jutman; Maksim Jenihhin (CoRR, 2025)