Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control. - Vivek Asthana; Malathi Kar; Jean Jimenez; Jean-Philippe Noel; Sébastien Haendler; Philippe Galy (ESSCIRC, 2013)

6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology. - Vivek Asthana; Malathi Kar; Jean Jimenez; Sébastien Haendler; Philippe Galy (ICICDT, 2013)