Efficient scan-based BIST scheme for low power testing of VLSI chips. - Malav Shah (ISLPED, 2006)

BIST Scheme for Low Heat Dissipation and Reduced Test Application Time. - Malav Shah; Dipankar Nagchoudhuri (VLSI-SoC, 2006)

Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test. - Amit Dutta; Malav Shah; G. Swathi; Rubin A. Parekhji (IOLTS, 2009)

Finding Cryptocurrency Attack Indicators Using Temporal Logic and Darkweb Data. - Mohammed Almukaynizi; Vivin Paliath; Malay Shah; Malav Shah; Paulo Shakarian (ISI, 2018)

Special Session: A Quality and Reliability Driven DFT and DFR Strategy for Automotive and Industrial Markets. - Malav Shah; Subhadeep Ghosh; Scott Martin (VTS, 2019)

Single Chip Traction Inverter System using High Performance and Real-time AM263 MCU. - Mihir Mody; Sean Murphy; Prithvi Shankar; VC Kumar; Mohammad Asif Farooqui; Malav Shah; Nikhil Sangani; Anita Pratti; Shailesh Ghotgalkar; Sriraj Chellappan; Stalin S. M.; Shivasharan Nagalikar; et al. (ICCE, 2023)

Single Chip Radar Processing for Object Detection. - Shivasharan Nagalikar; Mihir Mody; Ankur Baranwal; VC Kumar; Prithvi Shankar; Mohammad Asif Farooqui; Malav Shah; Nikhil Sangani; Y. C. Rakesh; Abhishek Karkisaval; Sriraj Chellappan; Stalin S. M.; et al. (ICCE, 2023)