Minimization of multioutput TANT networks for unlimited fan-in network model. - Marek A. Perkowski; Malgorzata Chrzanowska-Jeske; Tuhar Shah (ICCD, 1990)

Partitioning approach to find an exact solution to the fitting problem in an application-specific EPLD device. - Malgorzata Chrzanowska-Jeske; Steffen Goller (EURO-DAC, 1993)

An Architecture-driven Approach for the Fitting Problem in an Application-specific EPLD. - Malgorzata Chrzanowska-Jeske; Steffen Goller; Ingo Schäfer (ISCAS, 1993)

A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays. - Andisheh Sarabi; Ning Song; Malgorzata Chrzanowska-Jeske; Marek A. Perkowski (DAC, 1994)

Output Column Folding for Cellular-Architecture FPGAs. - Ning Song; Malgorzata Chrzanowska-Jeske (ISCAS, 1994)

Multiple-Valued-Input TANT Networks. - Marek A. Perkowski; Malgorzata Chrzanowska-Jeske (ISMVL, 1994)

An Exact Solution to the Fitting Problem in the Application Specific State Machine Device. - Marek A. Perkowski; Malgorzata Chrzanowska-Jeske; Edmund Pierzchala; Alan J. Coppola (J. Circuits Syst. Comput., 1994)

Layout synthesis for datapath designs. - Naveen Buddi; Malgorzata Chrzanowska-Jeske; Charles L. Saxe (EURO-DAC, 1995)

Tree restructuring approach to mapping problem in cellular-architecture FPGAs. - Naveen Ramineni; Malgorzata Chrzanowska-Jeske; Naveen Buddi (EURO-DAC, 1995)

Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions. - Marek A. Perkowski; Malgorzata Chrzanowska-Jeske; Andisheh Sarabi; Ingo Schäfer (VLSI Design, 1995)

A New Design Methodology for Two-Dimensional Logic Arrays. - Ning Song; Marek A. Perkowski; Malgorzata Chrzanowska-Jeske; Andisheh Sarabi (VLSI Design, 1995)

Synthesis approach to multi-level regular representation for combinational circuits. - Malgorzata Chrzanowska-Jeske; Chungping Guo (ICECS, 1996)

Variable ordering for regular layout representation. - Malgorzata Chrzanowska-Jeske; Yang Xu (ICECS, 1998)

Generalized symmetric and generalized pseudo-symmetric functions. - Malgorzata Chrzanowska-Jeske (ICECS, 1999)

Regular symmetric arrays for non-symmetric functions. - Malgorzata Chrzanowska-Jeske (ISCAS (1), 1999)

Logic Synthesis for a Regular Layout. - Malgorzata Chrzanowska-Jeske; Yang Xu; Marek A. Perkowski (VLSI Design, 1999)

Disjunctive Decomposition of Switching Functions Using Symmetry Information. - Malgorzata Chrzanowska-Jeske; Wei Wang; Jing Xia; Marcin Jeske (SBCCI, 2000)

Regular Realization of Symmetric Functions Using Reversible Logic. - Marek A. Perkowski; Malgorzata Chrzanowska-Jeske; Alan Mishchenko; Xiaoyu Song; Anas Al-Rabadi; Bart Massey; Pawel Kerntopf; Andrzej Buller; Lech Józwiak; Alan J. Coppola (DSD, 2001)

Generalized symmetric variables. - Malgorzata Chrzanowska-Jeske (ICECS, 2001)

A global approach to the variable ordering problem in PSBDDs. - Wei Wang; Malgorzata Chrzanowska-Jeske (ISCAS (5), 2001)

Combining evolution strategies with Lagrangian relaxation for constructing nonslicing VLSI floorplans with soft modules. - Malgorzata Chrzanowska-Jeske; Garrison W. Greenwood; Benyi Wang (IEEE Congress on Evolutionary Computation, 2002)

Board-level multiterminal net assignment. - Xiaoyu Song; William N. N. Hung; Alan Mishchenko; Malgorzata Chrzanowska-Jeske; Alan J. Coppola; Andrew A. Kennings (ACM Great Lakes Symposium on VLSI, 2002)

ELF-SP - evolutionary algorithm for non-slicing floorplans with soft modules. - Benyi Wang; Malgorzata Chrzanowska-Jeske; Garrison W. Greenwood (ICECS, 2002)

Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. - Faran Rafiq; Malgorzata Chrzanowska-Jeske; Hannah Honghua Yang; Naveed A. Sherwani (ISPD, 2002)

Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including Minimum ESOPs. - Malgorzata Chrzanowska-Jeske; Alan Mishchenko; Marek A. Perkowski (VLSI Design, 2002)

Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts. - Marek A. Perkowski; Bogdan J. Falkowski; Malgorzata Chrzanowska-Jeske; Rolf Drechsler (VLSI Design, 2002)

Core-based SoC test scheduling using evolutionary algorithm. - Yu Xia; Malgorzata Chrzanowska-Jeske; Benyi Wang (IEEE Congress on Evolutionary Computation, 2003)

Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints. - Yu Xia; Malgorzata Chrzanowska-Jeske; Benyi Wang; Marcin Jeske (ICCAD, 2003)

Floorplanning with performance-based clustering. - Malgorzata Chrzanowska-Jeske; Benyi Wang; Garrison W. Greenwood (ISCAS (4), 2003)

Graph-based approach to evaluate net routability of a floorplan. - Niwat Waropus; Rajendar Koltur; Malgorzata Chrzanowska-Jeske (ISCAS (5), 2003)

Integrated floorplanning with buffer/channel insertion for bus-based designs. - Faran Rafiq; Malgorzata Chrzanowska-Jeske; Hannah Honghua Yang; Marcin Jeske; Naveed A. Sherwani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Board-level multiterminal net assignment for the partial cross-bar architecture. - Xiaoyu Song; William N. N. Hung; Alan Mishchenko; Malgorzata Chrzanowska-Jeske; Andrew A. Kennings; Alan J. Coppola (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Substrate noise-aware floorplanning for mixed-signal SOCs. - Marcin Jeske; Grzegorz Blakiewicz; Malgorzata Chrzanowska-Jeske; Benyi Wang (ISCAS (2), 2004)

Generating random benchmark circuits for floorplanning. - Tao Wan; Malgorzata Chrzanowska-Jeske (ISCAS (5), 2004)

Prediction of interconnect net-degree distribution based on Rent's rule. - Tao Wan; Malgorzata Chrzanowska-Jeske (SLIP, 2004)

Substrate noise optimization in early floorplanning for mixed signal SOCs. - Grzegorz Blakiewicz; Marcin Jeske; Malgorzata Chrzanowska-Jeske (SoCC, 2004)

Substrate noise modeling in early floorplanning of MS-SOCs. - Grzegorz Blakiewicz; Marcin Jeske; Malgorzata Chrzanowska-Jeske; Jin S. Zhang (ASP-DAC, 2005)

Detecting support-reducing bound sets using two-cofactor symmetries. - Jin S. Zhang; Malgorzata Chrzanowska-Jeske; Alan Mishchenko; Jerry R. Burch (ASP-DAC, 2005)

Considering layout for test scheduling of core-based SoCs. - Yu Xia; Malgorzata Chrzanowska-Jeske (ICECS, 2005)

Modeling of substrate noise block properties for early prediction. - Grzegorz Blakiewicz; Malgorzata Chrzanowska-Jeske (ISCAS (3), 2005)

Synthesis for regularity using decision diagrams [logic IC synthesis and layout]. - Malgorzata Chrzanowska-Jeske; Alan Mishchenko (ISCAS (5), 2005)

Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. - Jin S. Zhang; Alan Mishchenko; Robert K. Brayton; Malgorzata Chrzanowska-Jeske (DAC, 2006)

Estimation of supply current spectrum for early noise evaluation. - Grzegorz Blakiewicz; Malgorzata Chrzanowska-Jeske (ISCAS, 2006)

Using simulation and satisfiability to compute flexibilities in Boolean networks. - Alan Mishchenko; Jin S. Zhang; Subarnarekha Sinha; Jerry R. Burch; Robert K. Brayton; Malgorzata Chrzanowska-Jeske (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Linear cofactor relationships in Boolean functions. - Jin S. Zhang; Malgorzata Chrzanowska-Jeske; Alan Mishchenko; Jerry R. Burch (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Supply current spectrum estimation of digital cores at early design. - Grzegorz Blakiewicz; Malgorzata Chrzanowska-Jeske (IET Circuits Devices Syst., 2007)

A novel net-degree distribution model and its application to floorplanning benchmark generation. - Tao Wan; Malgorzata Chrzanowska-Jeske (Integr., 2007)

Rectangular 3D wirelength distribution models. - Rajeev K. Nain; Rajarshi Ray 003; Malgorzata Chrzanowska-Jeske (ICECS, 2008)

Carbon nanotube circuit design choices in the presence of metallic tubes. - Rehman Ashraf; Malgorzata Chrzanowska-Jeske; Siva G. Narendra (ISCAS, 2008)

Optimization of active circuits for substrate noise suppression. - Grzegorz Blakiewicz; Malgorzata Chrzanowska-Jeske (ISCAS, 2008)

Placement-aware 3D Floorplanning. - Rajeev K. Nain; Malgorzata Chrzanowska-Jeske (ISCAS, 2009)

Yield enhancement by tube redundancy in CNFET-based circuits. - Rehman Ashraf; Rajeev K. Nain; Malgorzata Chrzanowska-Jeske; Siva G. Narendra (ICECS, 2010)

Yield improvement of 3D ICs in the presence of defects in through signal vias. - Rajeev K. Nain; Shantesh Pinge; Malgorzata Chrzanowska-Jeske (ISQED, 2010)

Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes. - Rehman Ashraf; Rajeev K. Nain; Malgorzata Chrzanowska-Jeske; Siva G. Narendra (NANOARCH, 2010)

Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs. - Rajeev K. Nain; Malgorzata Chrzanowska-Jeske (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Fast floorplanning for fixed-outline and nonrectangular regions. - Mohammad A. Ahmed; Shantesh Pinge; Malgorzata Chrzanowska-Jeske (ICECS, 2012)

TSV stress-aware performance and reliability analysis. - Muhammad Ali 006; Mohammad A. Ahmed; Malgorzata Chrzanowska-Jeske (ICECS, 2012)

Performance analysis of CNFET based circuits in the presence of fabrication imperfections. - Malgorzata Chrzanowska-Jeske; Rehman Ashraf; Rajeev K. Nain; Siva G. Narendra (ISCAS, 2012)

TSV capacitance aware 3-D floorplanning. - Mohammad A. Ahmed; Malgorzata Chrzanowska-Jeske (3DIC, 2013)

Just because we teach it does not mean they use it: Case of programming skills. - Branimir Pejcinovic; Melinda Holtzman; Malgorzata Chrzanowska-Jeske; Phillip K. Wong (FIE, 2013)

Fast floorplanning with placement constraints. - Shantesh Pinge; Rajeev K. Nain; Malgorzata Chrzanowska-Jeske (LASCAS, 2013)

3D floorplanning with nets-to-TSVs assignment. - Mohammad A. Ahmed; Sucheta Mohapatra; Malgorzata Chrzanowska-Jeske (ICECS, 2014)

Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes. - Muhammad Ali 006; Mohammad A. Ahmed; Malgorzata Chrzanowska-Jeske (ICECS, 2014)

Delay and power optimization with TSV-aware 3D floorplanning. - Mohammad A. Ahmed; Malgorzata Chrzanowska-Jeske (ISQED, 2014)

TSVs in early layout design exploration for 3D ICs. - Mohammad A. Ahmed; Malgorzata Chrzanowska-Jeske (LASCAS, 2014)

Dynamic nets-to-TSVs assignment in 3D floorplanning. - Mohammad A. Ahmed; Sucheta Mohapatra; Malgorzata Chrzanowska-Jeske (ISCAS, 2015)

Buffered Interconnects in 3D IC Layout Design. - Mohammad A. Ahmed; Sucheta Mohapatra; Malgorzata Chrzanowska-Jeske (SLIP, 2016)

Performance optimization and power efficiency in 3D IC with buffer insertion scheme. - Mohammad A. Ahmed; Sucheta Mohapatra; Malgorzata Chrzanowska-Jeske (SoCC, 2016)

Tutorial 2A: 3D integration - challenges and advantages. - Malgorzata Chrzanowska-Jeske; Jürgen Becker 001 (SoCC, 2016)

Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile. - Satya K. Vendra; Malgorzata Chrzanowska-Jeske (ISCAS, 2018)

Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. - Muhammad Ali 006; Mohammad A. Ahmed; Malgorzata Chrzanowska-Jeske (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Fast Thermal Goodness Evaluation of a 3D-IC Floorplan. - Satya K. Vendra; Malgorzata Chrzanowska-Jeske (ISQED, 2021)

Fast Buffer Count Estimation in 3D IC Floorplanning. - Sucheta Mohapatra; Satya K. Vendra; Malgorzata Chrzanowska-Jeske (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

RS3DPlace: Monolithic 3D IC placement using Reinforcement Learning and Simulated Annealing. - Abdullah Mansoor; Malgorzata Chrzanowska-Jeske (ISCAS, 2022)

SERS-3DPlace: Ensemble Reinforcement Learning for 3D Monolithic Placement. - Abdullah Mansoor; Malgorzata Chrzanowska-Jeske (ISCAS, 2024)