Single-Layer Routing for VLSI: Analysis and Algorithms. - Malgorzata Marek-Sadowska; Tom Tsan-Kuo Tarng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

Global Routing for Gate Array. - Jeong-Tyng Li; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

An Unconstrained Topological Via Minimization Problem for Two-Layer Routing. - Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

An Efficient Single-Row Routing Algorithm. - Tom Tsan-Kuo Tarng; Malgorzata Marek-Sadowska; Ernest S. Kuh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

Two-dimensional router for double layer layout. - Malgorzata Marek-Sadowska (DAC, 1985)

Pad Assignment for Power Nets in VLSI Circuits. - Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Automatic Sizing of Power/Ground (P/G) Networks in VLSI. - Rajiv Dutta; Malgorzata Marek-Sadowska (DAC, 1989)

Timing driven placement. - Malgorzata Marek-Sadowska; Shen Lin 001 (ICCAD, 1989)

Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic. - Fillia Makedon; Malgorzata Marek-Sadowska (ICCAL, 1989)

Delay and Area Optimization in Standard-Cell Design. - Shen Lin 001; Malgorzata Marek-Sadowska; Ernest S. Kuh (DAC, 1990)

Floorplanning with Pin Assignment. - Massoud Pedram; Malgorzata Marek-Sadowska; Ernest S. Kuh (ICCAD, 1990)

Pin assignment for improved performance in standard cell design. - Malgorzata Marek-Sadowska; Shen P. Lin (ICCD, 1990)

A fast and efficient algorithm for determining fanout trees in large networks. - Shen Lin 001; Malgorzata Marek-Sadowska (EURO-DAC, 1991)

SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits. - Shen Lin 001; Malgorzata Marek-Sadowska; Ernest S. Kuh (EURO-DAC, 1991)

The Crossing Distribution Problem. - Malgorzata Marek-Sadowska; Majid Sarrafzadeh (ICCAD, 1991)

Technology Mapping via Transformations of Function Graphs. - Shih-Chieh Chang; Malgorzata Marek-Sadowska (ICCD, 1992)

A New Accurate and Efficient Timing Simulator. - Shen Lin 001; Ernest S. Kuh; Malgorzata Marek-Sadowska (VLSI Design, 1992)

Switch box routing: a retrospective. - Malgorzata Marek-Sadowska (Integr., 1992)

Algorithm for wire sizing of Power and Ground Networks in VLSI Designs. - Robi Dutta; Malgorzata Marek-Sadowska (J. Circuits Syst. Comput., 1992)

Issues in Timing Driven Layout. - Malgorzata Marek-Sadowska (Algorithmic Aspects of VLSI Layout, 1993)

Graph based analysis of FPGA routing. - Yu-Liang Wu; Malgorzata Marek-Sadowska (EURO-DAC, 1993)

Efficient minimization algorithms for fixed polarity AND/XOR canonical networks. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (Great Lakes Symposium on VLSI, 1993)

Stepwise equivalent conductance circuit simulation technique. - Shen Lin 001; Ernest S. Kuh; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Layout Driven Logic Synthesis for FPGAs. - Shih-Chieh Chang; Kwang-Ting Cheng; Nam Sung Woo; Malgorzata Marek-Sadowska (DAC, 1994)

Boolean Matching Using Generalized Reed-Muller Forms. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (DAC, 1994)

Minimal Delay Interconnect Design Using Alphabetic Trees. - Ashok Vittal; Malgorzata Marek-Sadowska (DAC, 1994)

Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. - Shih-Chieh Chang; David Ihsin Cheng; Malgorzata Marek-Sadowska (EDAC-ETC-EUROASIC, 1994)

An Efficient Router for 2-D Field Programmable Gate Arrays. - Yu-Liang Wu; Malgorzata Marek-Sadowska (EDAC-ETC-EUROASIC, 1994)

On computational complexity of a detailed routing problem in two dimensional FPGAs. - Yu-Liang Wu; Shuji Tsukiyama; Malgorzata Marek-Sadowska (Great Lakes Symposium on VLSI, 1994)

Perturb and simplify: multi-level boolean network optimizer. - Shih-Chieh Chang; Malgorzata Marek-Sadowska (ICCAD, 1994)

Universal logic gate for FPGA design. - Chih-Chang Lin; Malgorzata Marek-Sadowska; Duane Gatlin (ICCAD, 1994)

Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (ISCAS, 1994)

On the Verification of Function Equivalence with unknown Input Correspondence. - David Ihsin Cheng; Malgorzata Marek-Sadowska (J. Circuits Syst. Comput., 1994)

Logic rectification and synthesis for engineering change. - Chih-Chang Lin; David Ihsin Cheng; Malgorzata Marek-Sadowska; Kuang-Chien Chen (ASP-DAC, 1995)

Routing on regular segmented 2-D FPGAs. - Yu-Liang Wu; Malgorzata Marek-Sadowska (ASP-DAC, 1995)

An Efficient Algorithm for Local Don't Care Sets Calculation. - Shih-Chieh Chang; Malgorzata Marek-Sadowska; Kwang-Ting Cheng (DAC, 1995)

Logic Synthesis for Engineering Change. - Chih-Chang Lin; Kuang-Chien Chen; Shih-Chieh Chang; Malgorzata Marek-Sadowska; Kwang-Ting Cheng (DAC, 1995)

Power Optimal Buffered Clock Tree Design. - Ashok Vittal; Malgorzata Marek-Sadowska (DAC, 1995)

Power Distribution Topology Design. - Ashok Vittal; Malgorzata Marek-Sadowska (DAC, 1995)

Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing. - Yu-Liang Wu; Malgorzata Marek-Sadowska (DAC, 1995)

Circuit partitioning with logic perturbation. - David Ihsin Cheng; Chih-Chang Lin; Malgorzata Marek-Sadowska (ICCAD, 1995)

Cost-free scan: a low-overhead scan path design methodology. - Chih-Chang Lin; Mike Tien-Chien Lee; Malgorzata Marek-Sadowska; Kuang-Chien Chen (ICCAD, 1995)

The crossing distribution problem [IC layout]. - Malgorzata Marek-Sadowska; Majid Sarrafzadeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

A New Hybrid Methodology for Power Estimation. - David Ihsin Cheng; Kwang-Ting Cheng; Deborah C. Wang; Malgorzata Marek-Sadowska (DAC, 1996)

Test Point Insertion: Scan Paths through Combinational Logic. - Chih-Chang Lin; Malgorzata Marek-Sadowska; Kwang-Ting Cheng; Mike Tien-Chien Lee (DAC, 1996)

Multilevel Logic Synthesis for Arithmetic Functions. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (DAC, 1996)

Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares. - Shih-Chieh Chang; Malgorzata Marek-Sadowska (ED&TC, 1996)

Sequential Permissible Functions and their Application to Circuit Optimization. - Chih-Chang Lin; Malgorzata Marek-Sadowska; Kuang-Chien Chen; Mike Tien-Chien Lee (ED&TC, 1996)

Logic Synthesis for Testability. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (Great Lakes Symposium on VLSI, 1996)

Fast Boolean optimization by rewiring. - Shih-Chieh Chang; Lukas P. P. P. van Ginneken; Malgorzata Marek-Sadowska (ICCAD, 1996)

Clock skew optimization for ground bounce control. - Ashok Vittal; Hein Ha; Forrest Brewer; Malgorzata Marek-Sadowska (ICCAD, 1996)

Generalized Reed-Muller Forms as a Tool to Detect Symmetries. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (IEEE Trans. Computers, 1996)

Perturb and simplify: multilevel Boolean network optimizer. - Shih-Chieh Chang; Malgorzata Marek-Sadowska; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. - Shih-Chieh Chang; Malgorzata Marek-Sadowska; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Graph based analysis of 2-D FPGA routing. - Yu-Liang Wu; Shuji Tsukiyama; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Not necessarily more switches more routability [sic.]. - Yu-Liang Wu; Douglas Chang; Malgorzata Marek-Sadowska; Shuji Tsukiyama (ASP-DAC, 1997)

A Test Synthesis Approach to Reducing BALLAST DFT Overhead. - Douglas Chang; Mike Tien-Chien Lee; Malgorzata Marek-Sadowska; Takashi Aikyo; Kwang-Ting Cheng (DAC, 1997)

Post-Layout Logic Restructuring for Performance Optimization. - Yi-Min Jiang; Angela Krstic; Kwang-Ting Cheng; Malgorzata Marek-Sadowska (DAC, 1997)

STARBIST: Scan Autocorrelated Random Pattern Generation. - Kun-Han Tsai; Sybille Hellebrand; Janusz Rajski; Malgorzata Marek-Sadowska (DAC, 1997)

Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs. - Douglas Chang; Malgorzata Marek-Sadowska (FPGA, 1997)

Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. - Stan Grygiel; Marek A. Perkowski; Malgorzata Marek-Sadowska; Tadeusz Luba; Lech Józwiak (ISMVL, 1997)

Decomposition of Multiple-Valued Relations . - Marek A. Perkowski; Malgorzata Marek-Sadowska; Lech Józwiak; Tadeusz Luba; Stan Grygiel; Miroslawa Nowicka; Rahul Malvi; Zhi Wang; Jin S. Zhang (ISMVL, 1997)

Scan-Encoded Test Pattern Generation for BIST. - Kun-Han Tsai; Malgorzata Marek-Sadowska; Janusz Rajski (ITC, 1997)

Boolean Functions Classification via Fixed Polarity Reed-Muller Forms. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (IEEE Trans. Computers, 1997)

Postlayout logic restructuring using alternative wires. - Shih-Chieh Chang; Kwang-Ting Cheng; Nam Sung Woo; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

On designing universal logic blocks and their application to FPGA design. - Chih-Chang Lin; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Crosstalk reduction for VLSI. - Ashok Vittal; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Low-power buffered clock tree design. - Ashok Vittal; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Routing for array-type FPGA's. - Yu-Liang Wu; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Functional Scan Chain Testing. - Douglas Chang; Kwang-Ting Cheng; Malgorzata Marek-Sadowska; Mike Tien-Chien Lee (DATE, 1998)

Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs. - Douglas Chang; Malgorzata Marek-Sadowska (FPGA, 1998)

A hybrid methodology for switching activities estimation. - David Ihsin Cheng; Kwang-Ting Cheng; Deborah C. Wang; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Test-point insertion: scan paths through functional logic. - Chih-Chang Lin; Malgorzata Marek-Sadowska; Kwang-Ting Cheng; Mike Tien-Chien Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Cost-free scan: a low-overhead scan path design. - Chih-Chang Lin; Malgorzata Marek-Sadowska; Mike Tien-Chien Lee; Kuang-Chien Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Power Distribution Synthesis for VLSI. - Ashok Vittal; Malgorzata Marek-Sadowska (VLSI Design, 1998)

Crosstalk Reduction by Transistor Sizing. - Tong Xiao; Malgorzata Marek-Sadowska (ASP-DAC, 1999)

Wave pipelining YADDs-a feasibility study. - Arindam Mukherjee 001; Malgorzata Marek-Sadowska; Stephen I. Long (CICC, 1999)

Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique. - Arindam Mukherjee 001; Ranganathan Sudhakar; Malgorzata Marek-Sadowska; Stephen I. Long (DAC, 1999)

Circuit clustering using graph coloring. - Amit Singh 001; Malgorzata Marek-Sadowska (ISPD, 1999)

STAR-ATPG: a high speed test pattern generator for large scan designs. - Kuo-Hui Tsai; Tompson; Janusz Rajski; Malgorzata Marek-Sadowska (ITC, 1999)

Modeling Crosstalk in Resistive VLSI Interconnections. - Ashok Vittal; Lauren Hui Chen; Malgorzata Marek-Sadowska; Kai-Ping Wang; Sherry Yang 003 (VLSI Design, 1999)

Circuit Optimization by Rewiring. - Shih-Chieh Chang; Lukas P. P. P. van Ginneken; Malgorzata Marek-Sadowska (IEEE Trans. Computers, 1999)

Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs. - Douglas Chang; Malgorzata Marek-Sadowska (IEEE Trans. Computers, 1999)

Logic synthesis for engineering change. - Chih-Chang Lin; Kuang-Chien Chen; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Crosstalk in VLSI interconnections. - Ashok Vittal; Lauren Hui Chen; Malgorzata Marek-Sadowska; Kai-Ping Wang; Sherry Yang 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Fast post-placement rewiring using easily detectable functional symmetries. - Chih-Wei Jim Chang; Chung-Kuan Cheng; Peter Suaris; Malgorzata Marek-Sadowska (DAC, 2000)

Wave-steering one-hot encoded FSMs. - Luca Macchiarulo; Malgorzata Marek-Sadowska (DAC, 2000)

Wave Steered FSMs. - Luca Macchiarulo; Shih-Ming Shu; Malgorzata Marek-Sadowska (DATE, 2000)

A novel high throughput reconfigurable FPGA architecture. - Amit Singh 001; Luca Macchiarulo; Arindam Mukherjee 001; Malgorzata Marek-Sadowska (FPGA, 2000)

Worst Delay Estimation in Crosstalk Aware Static Timing Analysis. - Tong Xiao; Malgorzata Marek-Sadowska (ICCD, 2000)

Aggressor alignment for worst-case coupling noise. - Lauren Hui Chen; Malgorzata Marek-Sadowska (ISPD, 2000)

Efficient Delay Calculation in Presence of Crosstalk. - Tong Xiao; Malgorzata Marek-Sadowska (ISQED, 2000)

OBDD Minimization Based on Two-Level Representation of Boolean Functions. - Yu-Liang Wu; Hongbing Fan; Malgorzata Marek-Sadowska; C. K. Wong (IEEE Trans. Computers, 2000)

Star test: the theory and its applications. - Kun-Han Tsai; Janusz Rajski; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques. - Chih-Wei Jim Chang; Kai Wang 011; Malgorzata Marek-Sadowska (DAC, 2001)

Latency and Latch Count Minimization in Wave Steered Circuits. - Amit Singh 001; Arindam Mukherjee 001; Malgorzata Marek-Sadowska (DAC, 2001)

Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification. - Tong Xiao; Malgorzata Marek-Sadowska (DAC, 2001)

In-place delay constrained power optimization using functional symmetries. - Chih-Wei Jim Chang; Bo Hu 006; Malgorzata Marek-Sadowska (DATE, 2001)

A Global Routing Technique for Wave-Steering Design Methodology. - Nobuo Funabiki; Amit Singh 001; Arindam Mukherjee 001; Malgorzata Marek-Sadowska (DSD, 2001)

Interconnect pipelining in a throughput-intensive FPGA architecture. - Amit Singh 001; Arindam Mukherjee 001; Malgorzata Marek-Sadowska (FPGA, 2001)

Who are the alternative wires in your neighborhood? (alternative wires identification without search). - Chih-Wei Jim Chang; Malgorzata Marek-Sadowska (ACM Great Lakes Symposium on VLSI, 2001)

Single-Pass Redundancy Addition and Removal. - Chih-Wei Jim Chang; Malgorzata Marek-Sadowska (ICCAD, 2001)

Interconnect Resource-Aware Placement for Hierarchical FPGAs. - Amit Singh 001; Ganapathy Parthasarathy; Malgorzata Marek-Sadowska (ICCAD, 2001)

Gate Sizing to Eliminate Crosstalk Induced Timing Violation. - Tong Xiao; Malgorzata Marek-Sadowska (ICCD, 2001)

Interconnect complexity-aware FPGA placement using Rent's rule. - Ganapathy Parthasarathy; Malgorzata Marek-Sadowska; Arindam Mukherjee 001; Amit Singh 001 (SLIP, 2001)

Aggressor alignment for worst-case crosstalk noise. - Lauren Hui Chen; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Coping with buffer delay change due to power and ground noise. - Lauren Hui Chen; Malgorzata Marek-Sadowska; Forrest Brewer (DAC, 2002)

Closed-Form Crosstalk Noise Metrics for Physical Design Applications. - Lauren Hui Chen; Malgorzata Marek-Sadowska (DATE, 2002)

Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. - Arindam Mukherjee 001; Kai Wang 011; Lauren Hui Chen; Malgorzata Marek-Sadowska (DATE, 2002)

Efficient circuit clustering for area and power reduction in FPGAs. - Amit Singh 001; Malgorzata Marek-Sadowska (FPGA, 2002)

ATPG-based logic synthesis: an overview. - Chih-Wei Jim Chang; Malgorzata Marek-Sadowska (ICCAD, 2002)

Congestion minimization during placement without estimation. - Bo Hu 006; Malgorzata Marek-Sadowska (ICCAD, 2002)

Incremental delay change due to crosstalk noise. - Lauren Hui Chen; Malgorzata Marek-Sadowska (ISPD, 2002)

FAR: fixed-points addition & relaxation based placement. - Bo Hu 006; Malgorzata Marek-Sadowska (ISPD, 2002)

Efficient Closed-Form Crosstalk Delay Metrics. - Lauren Hui Chen; Malgorzata Marek-Sadowska (ISQED, 2002)

FPGA interconnect planning. - Amit Singh 001; Malgorzata Marek-Sadowska (SLIP, 2002)

Efficient circuit clustering for area and power reduction in FPGAs. - Amit Singh 001; Ganapathy Parthasarathy; Malgorzata Marek-Sadowska (ACM Trans. Design Autom. Electr. Syst., 2002)

Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis. - Tong Xiao; Malgorzata Marek-Sadowska (VLSI Design, 2002)

Temporofunctional crosstalk noise analysis. - Donald Chai; Alex Kondratyev; Yajun Ran; Kenneth H. Tseng; Yosinori Watanabe; Malgorzata Marek-Sadowska (DAC, 2003)

Wire length prediction based clustering and its application in placement. - Bo Hu 006; Malgorzata Marek-Sadowska (DAC, 2003)

Gain-based technology mapping for discrete-size cell libraries. - Bo Hu 006; Yosinori Watanabe; Alex Kondratyev; Malgorzata Marek-Sadowska (DAC, 2003)

Crosstalk noise in FPGAs. - Yajun Ran; Malgorzata Marek-Sadowska (DAC, 2003)

Delay budgeting in sequential circuit with application on FPGA placement. - Chao-Yang Yeh; Malgorzata Marek-Sadowska (DAC, 2003)

Power/Ground Mesh Area Optimization Using Multigrid-Based Technique. - Kai Wang 011; Malgorzata Marek-Sadowska (DATE, 2003)

Minimum-Area Sequential Budgeting for FPGA. - Chao-Yang Yeh; Malgorzata Marek-Sadowska (ICCAD, 2003)

Multiple Fault Diagnosis Using n-Detection Tests. - Zhiyuan Wang; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (ICCD, 2003)

A crosstalk aware two-pin net router. - Ming-Fu Hsiao; Malgorzata Marek-Sadowska; Sao-Jie Chen (ISCAS (5), 2003)

Minimizing coupling jitter by buffer resizing for coupled clock networks. - Ming-Fu Hsiao; Malgorzata Marek-Sadowska; Sao-Jie Chen (ISCAS (5), 2003)

Synthesis and placement flow for gain-based programmable regular fabrics. - Bo Hu 006; Hailin Jiang; Qinghua Liu; Malgorzata Marek-Sadowska (ISPD, 2003)

Fine granularity clustering for large scale placement problems. - Bo Hu 006; Malgorzata Marek-Sadowska (ISPD, 2003)

Minimizing Inter-Clock Coupling Jitter. - Ming-Fu Hsiao; Malgorzata Marek-Sadowska; Sao-Jie Chen (ISQED, 2003)

Modeling Crosstalk Induced Delay. - Chung-Kuan Tsai; Malgorzata Marek-Sadowska (ISQED, 2003)

An Efficient and Effective Methodology on the Multiple Fault Diagnosis. - Zhiyuan Wang; Kun-Han Tsai; Malgorzata Marek-Sadowska; Janusz Rajski (ITC, 2003)

Wire length prediction in constraint driven placement. - Qinghua Liu; Bo Hu 006; Malgorzata Marek-Sadowska (SLIP, 2003)

Clock and Power Gating with Timing Closure. - Arindam Mukherjee 001; Malgorzata Marek-Sadowska (IEEE Des. Test Comput., 2003)

A new reasoning scheme for efficient redundancy addition and removal. - Chih-Wei Jim Chang; Ming-Fu Hsiao; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Buffer delay change in the presence of power and ground noise. - Lauren Hui Chen; Malgorzata Marek-Sadowska; Forrest Brewer (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Wave steering to integrate logic and physical syntheses. - Arindam Mukherjee 001; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2003)

PITIA: an FPGA for throughput-intensive applications. - Amit Singh 001; Arindam Mukherjee 001; Luca Macchiarulo; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Designing a via-configurable regular fabric. - Yajun Ran; Malgorzata Marek-Sadowska (CICC, 2004)

Pre-layout wire length and congestion estimation. - Qinghua Liu; Malgorzata Marek-Sadowska (DAC, 2004)

On designing via-configurable cell blocks for regular fabrics. - Yajun Ran; Malgorzata Marek-Sadowska (DAC, 2004)

Buffer sizing for clock power minimization subject to general skew constraints. - Kai Wang 011; Malgorzata Marek-Sadowska (DAC, 2004)

Eliminating False Positives in Crosstalk Noise Analysis. - Yajun Ran; Alex Kondratyev; Yosinori Watanabe; Malgorzata Marek-Sadowska (DATE, 2004)

Multilevel expansion-based VLSI placement with blockages. - Bo Hu 006; Malgorzata Marek-Sadowska (ICCAD, 2004)

An integrated design flow for a via-configurable gate array. - Yajun Ran; Malgorzata Marek-Sadowska (ICCAD, 2004)

The Magic of a Via-Configurable Regular Fabric. - Yajun Ran; Malgorzata Marek-Sadowska (ICCD, 2004)

Potential Slack Budgeting with Clock Skew Optimization. - Kai Wang 011; Malgorzata Marek-Sadowska (ICCD, 2004)

Diagnosis of Hold Time Defects. - Zhiyuan Wang; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (ICCD, 2004)

Clock network sizing via sequential linear programming with time-domain analysis. - Kai Wang 011; Malgorzata Marek-Sadowska (ISPD, 2004)

Pipelining Sequential Circuits with Wave Steering. - Luca Macchiarulo; Shih-Min Shu; Malgorzata Marek-Sadowska (IEEE Trans. Computers, 2004)

Fast postplacement optimization using functional symmetries. - Chih-Wei Jim Chang; Ming-Fu Hsiao; Bo Hu 006; Kai Wang 011; Malgorzata Marek-Sadowska; Chung-Kuan Cheng; Sao-Jie Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Fine granularity clustering-based placement. - Bo Hu 006; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Individual wire-length prediction with application to timing-driven placement. - Qinghua Liu; Bo Hu 006; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Sequential delay budgeting with interconnect prediction. - Chao-Yang Yeh; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Skew-programmable clock design for FPGA and skew-aware placement. - Chao-Yang Yeh; Malgorzata Marek-Sadowska (FPGA, 2005)

Clock skew bounds estimation under power supply and process variations. - Hailin Jiang; Kai Wang 011; Malgorzata Marek-Sadowska (ACM Great Lakes Symposium on VLSI, 2005)

A congestion-driven placement framework with local congestion prediction. - Qinghua Liu; Malgorzata Marek-Sadowska (ACM Great Lakes Symposium on VLSI, 2005)

Timing-aware power noise reduction in layout. - Chao-Yang Yeh; Malgorzata Marek-Sadowska (ICCAD, 2005)

Benefits and Costs of Power-Gating Technique. - Hailin Jiang; Malgorzata Marek-Sadowska; Sani R. Nassif (ICCD, 2005)

Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement. - Qinghua Liu; Malgorzata Marek-Sadowska (ICCD, 2005)

mFAR: fixed-points-addition-based VLSI placement algorithm. - Bo Hu 006; Yue Zeng; Malgorzata Marek-Sadowska (ISPD, 2005)

Wire length prediction-based technology mapping and fanout optimization. - Qinghua Liu; Malgorzata Marek-Sadowska (ISPD, 2005)

An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis. - Chung-Kuan Tsai; Malgorzata Marek-Sadowska (ISQED, 2005)

Multilevel fixed-point-addition-based VLSI placement. - Bo Hu 006; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A study of netlist structure and placement efficiency. - Qinghua Liu; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Eliminating false positives in crosstalk noise analysis. - Yajun Ran; Alex Kondratyev; Kenneth H. Tseng; Yosinori Watanabe; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

On-chip power-supply network optimization using multigrid-based technique. - Kai Wang 011; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Delay-fault diagnosis using timing information. - Zhiyuan Wang; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

General skew constrained clock network sizing based on sequential linear programming. - Kai Wang 011; Yajun Ran; Hailin Jiang; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Power/ground supply network optimization for power-gating. - Hailin Jiang; Malgorzata Marek-Sadowska (ICCD, 2006)

Delay Fault Diagnosis for Non-Robust Test. - Vishal J. Mehta; Malgorzata Marek-Sadowska; Zhiyuan Wang; Kun-Han Tsai; Janusz Rajski (ISQED, 2006)

Analysis of Process Variation's Effect on SRAM's Read Stability. - Chung-Kuan Tsai; Malgorzata Marek-Sadowska (ISQED, 2006)

Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. - Vishal J. Mehta; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (ITC, 2006)

Semi-Individual Wire-Length Prediction With Application to Logic Synthesis. - Qinghua Liu; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Analysis and methodology for multiple-fault diagnosis. - Zhiyuan Wang; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Designing via-configurable logic blocks for regular fabric. - Yajun Ran; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics. - Yajun Ran; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2006)

mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement. - Bo Hu 006; Malgorzata Marek-Sadowska (Modern Circuit Placement, 2007)

OPC-Free and Minimally Irregular IC Design Style. - Wojciech Maly; Yi-Wei Lin; Malgorzata Marek-Sadowska (DAC, 2007)

An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. - Yu-Shih Su; Da-Chung Wang; Shih-Chieh Chang; Malgorzata Marek-Sadowska (DAC, 2007)

Engineering change using spare cells with constant insertion. - Yu-Min Kuo; Ya-Ting Chang; Shih-Chieh Chang; Malgorzata Marek-Sadowska (ICCAD, 2007)

Analysis and optimization of power-gated ICs with multiple power gating configurations. - Aida Todri; Malgorzata Marek-Sadowska; Shih-Chieh Chang (ICCAD, 2007)

Electromigration and voltage drop aware power grid optimization for power gated ICs. - Aida Todri; Shih-Chieh Chang; Malgorzata Marek-Sadowska (ISLPED, 2007)

Power-Gating Aware Floorplanning. - Hailin Jiang; Malgorzata Marek-Sadowska (ISQED, 2007)

Timing-Aware Power-Noise Reduction in Placement. - Chao-Yang Yeh; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Power gating scheduling for power/ground noise reduction. - Hailin Jiang; Malgorzata Marek-Sadowska (DAC, 2008)

Power supply noise aware workload assignment for multi-core systems. - Aida Todri; Malgorzata Marek-Sadowska; Joseph N. Kozhaya (ICCAD, 2008)

Is there always performance overhead for regular fabric? - Yi-Wei Lin; Malgorzata Marek-Sadowska; Wojciech Maly; Andrzej Pfitzner; Dominik Kasprowicz (ICCD, 2008)

ECO-Map: Technology remapping for post-mask ECO using simulated annealing. - Nilesh Modi; Malgorzata Marek-Sadowska (ICCD, 2008)

A study of reliability issues in clock distribution networks. - Aida Todri; Malgorzata Marek-Sadowska (ICCD, 2008)

Timing analysis considering IR drop waveforms in power gating designs. - Shih-Hung Weng; Yu-Min Kuo; Shih-Chieh Chang; Malgorzata Marek-Sadowska (ICCD, 2008)

Improving the Resolution of Single-Delay-Fault Diagnosis. - Vishal J. Mehta; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Electromigration study of power-gated grids. - Aida Todri; Malgorzata Marek-Sadowska (ISLPED, 2009)

Transistor-level layout of high-density regular circuits. - Yi-Wei Lin; Malgorzata Marek-Sadowska; Wojciech Maly (ISPD, 2009)

A study of decoupling capacitor effectiveness in power and ground grid networks. - Aida Todri; Malgorzata Marek-Sadowska; Francois Maire; Christophe Matheron (ISQED, 2009)

Spare Cells With Constant Insertion for Engineering Change. - Yu-Min Kuo; Ya-Ting Chang; Shih-Chieh Chang; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Timing-Aware Multiple-Delay-Fault Diagnosis. - Vishal J. Mehta; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Performance study of VeSFET-based, high-density regular circuits. - Yi-Wei Lin; Malgorzata Marek-Sadowska; Wojciech Maly (ISPD, 2010)

Statistical static timing analysis flow for transistor level macros in a microprocessor. - Vivek S. Nandakumar; David Newmark; Yaping Zhan; Malgorzata Marek-Sadowska (ISQED, 2010)

On-chip em-sensitive interconnect structures. - Di-An Li; Malgorzata Marek-Sadowska; Bill Lee (SLIP, 2010)

Layout Generator for Transistor-Level High-Density Regular Circuits. - Yi-Wei Lin; Malgorzata Marek-Sadowska; Wojciech Maly (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Rapid layout pattern classification. - Jen-Yi Wuu; Fedor G. Pikus; Andres J. Torres; Malgorzata Marek-Sadowska (ASP-DAC, 2011)

Layout effects in fine grain 3D integrated regular microprocessor blocks. - Vivek S. Nandakumar; Malgorzata Marek-Sadowska (DAC, 2011)

Variation-aware electromigration analysis of power/ground networks. - Di-An Li; Malgorzata Marek-Sadowska (ICCAD, 2011)

Low power, high throughput network-on-chip fabric for 3D multicore processors. - Vivek S. Nandakumar; Malgorzata Marek-Sadowska (ICCD, 2011)

On old and new routing problems. - Malgorzata Marek-Sadowska (ISPD, 2011)

Metrics for characterizing machine learning-based hotspot detection methods. - Jen-Yi Wuu; Fedor G. Pikus; Malgorzata Marek-Sadowska (ISQED, 2011)

On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits. - Yi-Wei Lin; Malgorzata Marek-Sadowska; Wojciech Maly (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Performance Optimization Using Variable-Latency Design Style. - Yu-Shih Su; Da-Chung Wang; Shih-Chieh Chang; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Reliability Analysis and Optimization of Power-Gated ICs. - Aida Todri; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Power Delivery for Multicore Systems. - Aida Todri; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Can pin access limit the footprint scaling? - Xiang Qiu; Malgorzata Marek-Sadowska (DAC, 2012)

Vertical Slit Field Effect Transistor in ultra-low power applications. - Xiang Qiu; Malgorzata Marek-Sadowska; Wojciech Maly (ISQED, 2012)

Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs. - Jen-Yi Wuu; Mark Simmons; Malgorzata Marek-Sadowska (ISQED, 2012)

A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures. - Vivek S. Nandakumar; Malgorzata Marek-Sadowska (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure. - Xiang Qiu; Malgorzata Marek-Sadowska; Wojciech Maly (ISPD, 2013)

SRAM bit-line electromigration mechanism and its prevention scheme. - Zhong Guan; Malgorzata Marek-Sadowska; Sani R. Nassif (ISQED, 2013)

Routing Challenges for Designs With Super High Pin Density. - Xiang Qiu; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs. - Vivek S. Nandakumar; Malgorzata Marek-Sadowska (DAC, 2014)

Statistical analysis of process variation induced SRAM electromigration degradation. - Zhong Guan; Malgorzata Marek-Sadowska; Sani R. Nassif (ISQED, 2014)

Estimating true worst currents for power grid electromigration analysis. - Di-An Li; Malgorzata Marek-Sadowska (ISQED, 2014)

On Optimal Kernel Size for Integrated CPU-GPUs - A Case Study. - Vivek S. Nandakumar; Malgorzata Marek-Sadowska (IEEE Comput. Archit. Lett., 2014)

Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure. - Xiang Qiu; Malgorzata Marek-Sadowska; Wojciech P. Maly (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Blech Effect in Interconnects: Applications and Design Guidelines. - Ali Abbasinasab; Malgorzata Marek-Sadowska (ISPD, 2015)

Machine Learning in Simulation-Based Analysis. - Li-C. Wang; Malgorzata Marek-Sadowska (ISPD, 2015)

A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures. - Di-An Li; Malgorzata Marek-Sadowska; Sani R. Nassif (IEEE Trans. Very Large Scale Integr. Syst., 2015)

T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool. - Di-An Li; Malgorzata Marek-Sadowska; Sani R. Nassif (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips. - Xiang Qiu; Malgorzata Marek-Sadowska; Wojciech P. Maly (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluation. - Zhong Guan; Malgorzata Marek-Sadowska (ICCAD, 2016)

Making split-fabrication more secure. - Ping-Lin Yang; Malgorzata Marek-Sadowska (ICCAD, 2016)

A fast, fully verifiable, and hardware predictable ASIC design methodology. - Ping-Lin Yang; Malgorzata Marek-Sadowska (ICCD, 2016)

AFD-based method for signal line EM reliability evaluation. - Zhong Guan; Malgorzata Marek-Sadowska (ISQED, 2016)

Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence. - Zhong Guan; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2016)

RAIN: a tool for reliability assessment of interconnect networks - physics to software. - Ali Abbasinasab; Malgorzata Marek-Sadowska (DAC, 2018)

High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators. - Ping-Lin Yang; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration. - Ali Abbasinasab; Malgorzata Marek-Sadowska (ACM Great Lakes Symposium on VLSI, 2019)

ISPD 2023 Lifetime Achievement Award Bio. - Malgorzata Marek-Sadowska (ISPD, 2023)