A modular simulation framework for architectural exploration of on-chip interconnection networks. - Tim Kogel; Malte Doerper; Andreas Wieferink; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Serge Goossens (CODES+ISSS, 2003)

Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. - Tim Kogel; Malte Doerper; Torsten Kempf; Andreas Wieferink; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (SAMOS, 2004)

Early ISS Integration into Network-on-Chip Designs. - Andreas Wieferink; Malte Doerper; Tim Kogel; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (SAMOS, 2004)

A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. - Torsten Kempf; Malte Doerper; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Tim Kogel; Bart Vanthournout (DATE, 2005)

Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. - Tim Kogel; Malte Doerper; Torsten Kempf; Andreas Wieferink; Rainer Leupers; Heinrich Meyr (Int. J. Embed. Syst., 2008)