Evaluation of hardware and software implementations for NIST finalist and fourth-round post-quantum cryptography KEMs. - Mamatha Bandaru; Sudha Ellison Mathe; Chirawat Wattanapanich (Comput. Electr. Eng., 2024)

FPGA based high speed parallel modular polynomial multiplier for lattice based cryptosystems. - Mamatha Bandaru; Sudha Ellison Mathe (Comput. Electr. Eng., 2025)