Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFET. - Mamidala Jagadesh Kumar; Vikram Verma (IEEE Trans. Reliab., 2002)

A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design. - Mamidala Jagadesh Kumar; D. Venkateshrao (VLSI Design, 2003)

2D-simulation and analysis of lateral SiC N-emitter SiGe P-base Schottky metal-collector (NPM) HBT on SOI. - Mamidala Jagadesh Kumar; Linga Reddy Cenkeramaddi (Microelectron. Reliab., 2003)

A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors. - Mamidala Jagadesh Kumar; Vinod Parihar (VLSI Design, 2004)

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study. - G. Venkateshwar Reddy; Mamidala Jagadesh Kumar (Microelectron. J., 2004)

Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation. - Mamidala Jagadesh Kumar; Vivek Venkataraman; Susheel Nawal (VLSI Design, 2007)

A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications. - Radhakrishnan Sithanandam; Mamidala Jagadesh Kumar (VLSI Design, 2010)

Modeling of Partially Depleted SOI DEMOSFETs with a Sub-circuit Utilizing the HiSIM-HV Compact Model. - Tarun Kumar Agarwal; Mamidala Jagadesh Kumar (VLSI Design, 2012)

DC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion Regions. - Rajat Vishnoi; Pratyush Panday; Mamidala Jagadesh Kumar (VLSID, 2017)

Comprehensive Analysis of Gate-Induced Drain Leakage in Emerging FET Architectures: Nanotube FETs Versus Nanowire FETs. - Shubham Sahay; Mamidala Jagadesh Kumar (IEEE Access, 2017)

Double gate symmetric tunnel FET: investigation and analysis. - Sindhu Ramaswamy; Mamidala Jagadesh Kumar (IET Circuits Devices Syst., 2017)

Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study. - Aakash Kumar Jain; Mamidala Jagadesh Kumar (IEEE Access, 2020)

Physical Insights into the Leakage Mechanisms Governing the Scaling Trends in 4H-SiC Based Junctionless FETs. - Jaspreet Singh; Aakash Kumar Jain; Mamidala Jagadesh Kumar (VLSID, 2025)