250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture. - Yasuhiro Takai; Mamoru Nagase; Mamoru Kitamura; Yasuji Koshikawa; Naoyuki Yoshida; Yasuaki Kobayashi; Takashi Obara; Yukio Fukuzo; Hiroshi Watanabe (IEEE J. Solid State Circuits, 1994)