Improved reslicing by voxel-project-method. - Mamoru Nakanishi (Syst. Comput. Jpn., 1995)

Real-time 3D Feature Extraction Hardware Algorithm with Feature Point Matching Capability. - Eiichi Hosoya; Takeshi Ogura; Mamoru Nakanishi (MVA, 1996)

Real-time Hough Transform Based Circular Shape Extraction. - Mahmoud Méribout; Takeshi Ogura; Mamoru Nakanishi (MVA, 1996)

Real-Time Line Extraction Using a Highly Parallel Hough Tranform Board. - Mamoru Nakanishi; Takeshi Ogura (ICIP (2), 1997)

Real-time 3D Reconstruction System using CAM-based Highly Parallel Processing Board. - Eiichi Hosoya; Mamoru Nakanishi; Takeshi Ogura (Three-Dimensional Image Capture and Applications, 1998)

A Real-Time Image Segmentation on a Massively Parallel Architecture. - Mahmoud Méribout; Mamoru Nakanishi; Takeshi Ogura (Real Time Imaging, 1999)

Hough Transform Algorithm for Three-Dimensional Segment Extraction and its Parallel Hardware Implementation. - Mahmoud Méribout; Mamoru Nakanishi; Eiichi Hosoya; Takeshi Ogura (Comput. Vis. Image Underst., 2000)

Real-time CAM-based Hough transform algorithm and its performance evaluation. - Mamoru Nakanishi; Takeshi Ogura (Mach. Vis. Appl., 2000)

On using the CAM concept for parametric curve extraction. - Mahmoud Méribout; Takeshi Ogura; Mamoru Nakanishi (IEEE Trans. Image Process., 2000)

A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification. - Koji Fujii; Mamoru Nakanishi; Satoshi Shigematsu; Hiroki Morimura; Takahiro Hatano; Namiko Ikeda; Toshishige Shimamura; Yukio Okazaki; Hakaru Kyuragi (CICC, 2002)

Fingerprint Image Enhancement by Pixel-Parallel Processing. - Namiko Ikeda; Mamoru Nakanishi; Koji Fujii; Takahiro Hatano; Satoshi Shigematsu; Takuya Adachi; Yukio Okazaki; Hakaru Kyuragi (ICPR (3), 2002)

A parallel algorithm for real-time object recognition. - Mahmoud Méribout; Mamoru Nakanishi; Takeshi Ogura (Pattern Recognit., 2002)

Accurate and Real-time Image Processing on a New PC-compatible Board. - Mahmoud Méribout; Mamoru Nakanishi; Takeshi Ogura (Real Time Imaging, 2002)

A robust hardware algorithm for real-time object tracking in video sequences. - Mahmoud Méribout; Lazhar Khriji; Mamoru Nakanishi (Real Time Imaging, 2004)

A New Real Time Object Segmentation and Tracking Algorithm and its Parallel Hardware Architecture. - Mahmoud Méribout; Mamoru Nakanishi (J. VLSI Signal Process., 2005)

Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier. - Satoshi Shigematsu; Koji Fujii; Hiroki Morimura; Takahiro Hatano; Mamoru Nakanishi; Namiko Ikeda; Toshishige Shimamura; Katsuyuki Machida; Yukio Okazaki; Hakaru Kyuragi (IEICE Trans. Electron., 2006)

Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI. - Satoshi Shigematsu; Hiroki Morimura; Toshishige Shimamura; Takahiro Hatano; Namiko Ikeda; Yukio Okazaki; Katsuyuki Machida; Mamoru Nakanishi (IEICE Trans. Electron., 2007)

A Fingerprint Sensor with Impedance Sensing for Fraud Detection. - Toshishige Shimamura; Hiroki Morimura; Nobuhiro Shimoyama; Tomomi Sakata; Satoshi Shigematsu; Katsuyuki Machida; Mamoru Nakanishi (ISSCC, 2008)

Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs. - Toshishige Shimamura; Hiroki Morimura; Satoshi Shigematsu; Mamoru Nakanishi; Katsuyuki Machida (IEEE J. Solid State Circuits, 2010)

A 22-Gb/s and over-33-mega-frame/s throughput bridge-function unit in a low-latency OLT LSI for the coexistence of 10G-EPON and GE-PON. - Shoko Ohteru; Tomoaki Kawamura; Hiroki Suto; Masami Urano; Mamoru Nakanishi; Tsugumichi Shibata (A-SSCC, 2011)

10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control. - Sadayuki Yasuda; Takahiro Hatano; Hiroki Suto; Masami Urano; Mamoru Nakanishi; Tsugumichi Shibata (ISOCC, 2011)

Extendable point-to-multi-point protocol processor for 10G-EPON MAC SoCs. - Naoki Miura; Akihiko Miyazaki; Junichi Kato; Nobuyuki Tanaka; Masami Urano; Mamoru Nakanishi; Tsugumichi Shibata (ISCAS, 2012)

Evaluation of advanced pixel-level snakes on cellular hardware platform. - Matsui Takao; Tomohiro Fujita; Tsuji Yuji; Takeshi Kumaki; Mamoru Nakanishi; Takeshi Ogura (NEWCAS, 2013)

Cellular automaton based pixel-level snakes. - Tomohiro Fujita; Syo Sawada; Kaihei Iwanaga; Takeshi Kumaki; Mamoru Nakanishi; Takeshi Ogura (NEWCAS, 2014)

An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU. - Ryota Takasu; Yoichi Tomioka; Yutaro Ishigaki; Ning Li; Tsugumichi Shibata; Mamoru Nakanishi; Hitoshi Kitazawa (IEICE Trans. Electron., 2014)

Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip. - Naoki Miura; Akihiko Miyazaki; Junichi Kato; Nobuyuki Tanaka; Satoshi Shigematsu; Masami Urano; Mamoru Nakanishi; Tsugumichi Shibata (IEICE Trans. Electron., 2015)