Microarchitecture Support for Reducing Branch Penalty in a Supercscaler Processor. - Mamoru Sakamoto; Toyohiko Yoshida; Yasuhiro Nunomura; Yukihiko Shimazu (ICCD, 1996)

Evaluation of processor code efficiency for embedded systems. - Morgan Hirosuke Miki; Mamoru Sakamoto; Shingo Miyamoto; Yoshinori Takeuchi; Toyohiko Yoshida; Isao Shirakawa (ICS, 2001)

Embedded implementation of acoustic field enhancement for stereo headphones. - Nobuyuki Iwanaga; Wataru Kobayashi; Kazuhiko Furuya; Mamoru Sakamoto; Takao Onoye; Isao Shirakawa (APCCAS (1), 2002)

Code Efficiency Evaluation for Embedded Processors. - Morgan Hirosuke Miki; Mamoru Sakamoto; Shingo Miyamoto; Yoshinori Takeuchi; Toyohiko Yoshida; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A modeling method of a rule based control system with hierarchical Petri net. - Mamoru Sakamoto; Toshiyuki Miyamoto; Sadatoshi Kumagai (ISCAS (1), 2005)