A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory. - Satoshi Kaneko; Hiroyuki Kondo; Norio Masui; Koichi Ishimi; Teruyuki Itou; Masayuki Satou; Naoto Okumura; Yukari Takata; Hirokazu Takata; Mamoru Sakugawa; Takashi Higuchi; Sugako Ohtani; et al. (IEEE J. Solid State Circuits, 2004)

High frequency band dispersed-tone power line communication modem for networked appliances. - Hitoshi Kubota; Kazumasa Suzuki; Isamu Kawakimi; Mamoru Sakugawa; Hiroyuki Kondo (IEEE Trans. Consumer Electron., 2006)

Heterogeneous multicore SoC for secure multimedia applications. - Hiroyuki Kondo; Masami Nakajima; Sugako Otani; Osamu Yamamoto; Norio Masui; Naoto Okumura; Mamoru Sakugawa; Masaya Kitao; Koichi Ishimi; Masayuki Sato; Fumitaka Fukuzawa; Kazuhiro Inaoka; et al. (CICC, 2008)

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors. - Hiroyuki Kondo; Masami Nakajima; Norio Masui; Sugako Otani; Naoto Okumura; Yukari Takata; Takashi Nasu; Hirokazu Takata; Takashi Higuchi; Mamoru Sakugawa; Hayato Fujiwara; Kazuya Ishida; et al. (IEEE J. Solid State Circuits, 2008)

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications. - Hiroyuki Kondo; Sugako Otani; Masami Nakajima; Osamu Yamamoto; Norio Masui; Naoto Okumura; Mamoru Sakugawa; Masaya Kitao; Koichi Ishimi; Masayuki Sato; Fumitaka Fukuzawa; Satoshi Imasu; et al. (IEEE J. Solid State Circuits, 2009)

System performance and energy consumption improvement methodology by delay adjustable synchronizer. - Masanori Kurimoto; Yasuhiko Takahashi; Yuji Fujiwara; Mamoru Sakugawa; Souichi Kobayashi; Hiroyuki Kondo (A-SSCC, 2011)