An input test pattern for characterization of a full-adder and n-bit ripple carry adder. - Manan Mewada; Mazad Zaveri (ICACCI, 2016)

A low-power high-speed hybrid full adder. - Manan Mewada; Mazad Zaveri (VDAT, 2016)

Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions. - Manan Mewada; Mazad Zaveri; Anurag Lakhlani (VDAT, 2017)

Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures. - Manan Mewada; Mazad Zaveri; Rajesh Amratlal Thakker (Integr., 2019)