Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC. - Manas Kumar Hati; Tarun Kanti Bhattacharyya (ISVLSI, 2011)

A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL. - Manas Kumar Hati; Tarun Kanti Bhattacharyya (VDAT, 2012)

A 55-mW 300MS/s 8-bit CMOS Parallel Pipeline ADC. - Manas Kumar Hati; Tarun Kanti Bhattacharyya (VLSI Design, 2012)

A high o/p resistance, wide swing and perfect current matching charge pump having switching circuit for PLL. - Manas Kumar Hati; Tarun Kanti Bhattacharyya (Microelectron. J., 2013)

A 10-b, 500 MSPS current steering CMOS DAC with a switching current cell and high SFDR value. - Manas Kumar Hati; Tarun Kanti Bhattacharyya (APCCAS, 2014)

Efficient design technique for pulse swallow based fractional-N frequency divider. - Manas Kumar Hati; Tarun Kanti Bhattacharyya (ISCAS, 2015)

A fast automatic frequency and amplitude control LC-VCO circuit with noise filtering technique for a fractional-N PLL frequency synthesizer. - Manas Kumar Hati; Tarun Kanti Bhattacharyya (Microelectron. J., 2016)

A fast and efficient constant loop bandwidth with proposed PFD and pulse swallow divider circuit in ΔΣ fractional-N PLL frequency synthesizer. - Manas Kumar Hati; Tarun Kanti Bhattacharyya (Microelectron. J., 2017)

A High Power GaN MMIC 36.5 Watt X Band Power Amplifier. - Manas Kumar Hati; Tarun Kanti Bhattacharyya (TENCON, 2018)

A New Open Loop Linearization Technique for Power Amplifier Circuit in MMIC for 5G Wireless Backhaul Application. - Manas Kumar Hati; Tarun Kanti Bhattacharyya (TENCON, 2018)

Phase noise analysis of proposed PFD and CP switching circuit and its advantages over various PFD/CP switching circuits in phase-locked loops. - Manas Kumar Hati; Tarun Kanti Bhattacharyya (Integr., 2018)

A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation. - Manas Kumar Hati; Tarun Kanti Bhattacharyya (Integr., 2019)