Systematic Construction of Resistor Ladder Network for N-ary DACs. - Manato Hirai; Shuhei Yamamoto; Hirotaka Arai; Anna Kuwana; Hiroshi Tanimoto; Yuji Gendai; Haruo Kobayashi 001 (ASICON, 2019)

Digital-to-Analog Converter Architectures Based on Polygonal and Prime Numbers. - Yuanyang Du; Xueyan Bai; Manato Hirai; Shuhei Yamamoto; Anna Kuwana; Haruo Kobayashi 001; Kazuyoshi Kubo (ISOCC, 2020)

Nonlinearity Analysis of Resistive Ladder-Based Current-Steering Digital-to-Analog Converter. - Manato Hirai; Hiroshi Tanimoto; Yuji Gendai; Shuhei Yamamoto; Anna Kuwana; Haruo Kobayashi 001 (ISOCC, 2020)

Classical Mathematics and Analog/Mixed-Signal IC Design. - Haruo Kobayashi 001; Xueyan Bai; Yujie Zhao; Shuhei Yamamoto; Dan Yao; Manato Hirai; Jianglin Wei; Shogo Katayama; Anna Kuwana (ASICON, 2021)

Back to the Analog Neural Network and Linear Circuit Theory. - Haruo Kobayashi 001; Manato Hirai; Kakeru Otomo; Shogo Katayama; Xueyan Bai; Masashi Chiba; Zifei Xu; Dan Yao; Lengkhang Nengvang; Minh Tri Tran 001; Kanji Yoshihiro; Anna Kuwana; et al. (ASICON, 2023)