A Fast Sorting Algorithm for VLSI. - Hans-Werner Lang; Manfred Schimmler; Hartmut Schmeck; Heiko Schröder 001 (ICALP, 1983)

A Method for Realistic Comparisons of Sorting Algorithms for VLSI. - Hans-Werner Lang; Manfred Schimmler; Hartmut Schmeck; Heiko Schröder 001 (FODO, 1985)

Systolic Sorting on a Mesh-Connected Network. - Hans-Werner Lang; Manfred Schimmler; Hartmut Schmeck; Heiko Schröder 001 (IEEE Trans. Computers, 1985)

The instruction systolic array and its relation to other models of parallel computers. - Manfred Kunde; Hans-Werner Lang; Manfred Schimmler; Hartmut Schmeck; Heiko Schröder 001 (Parallel Comput., 1988)

A simple systolic method to find all bridges of an undirected graph. - Manfred Schimmler; Heiko Schröder 001 (Parallel Comput., 1989)

A Correction Network for N-Sorters. - Manfred Schimmler; Christoph Starke 001 (SIAM J. Comput., 1989)

Systolic algorithm for tensor products of matrices: implementation and applications. - E. V. Krishnamurthy; Manfred Kunde; Manfred Schimmler; Heiko Schröder 001 (Parallel Comput., 1990)

A Reconfigurable Instruction Systolic Array. - Michael Phieler; Manfred Schimmler; Hartmut Schmeck (Fault-Tolerant Computing Systems, 1991)

A Fault Tolerant and High Speed Instruction Systolic Array. - Manfred Schimmler; Hartmut Schmeck (VLSI, 1991)

Parallel strong orientation on a mesh connected computer. - Manfred Schimmler (Parallel Comput., 1991)

Graphenalgorithmen auf gitterverbundenen Prozessorfeldern. - Manfred Schimmler (1991)

The Instruction Systolic Array - Implementation of a Low-Cost Parallel Architecture as Add-On Board for Personal Computers. - Manfred Schimmler; Hans-Werner Lang; Rüdiger Maaß (HPCN, 1994)

Morphological Hough Transform on the Instruction Systolic Array. - Bertil Schmidt; Manfred Schimmler; Heiko Schröder 001 (Euro-Par, 1997)

Long Operand Arithmetic on Instruction Systolic Computer Architectures and Its Application in RSA Cryptography. - Bertil Schmidt; Manfred Schimmler; Heiko Schröder 001 (Euro-Par, 1998)

A Parallel Accelerator Architecture for Multimedia Video Compression. - Bertil Schmidt; Manfred Schimmler (Euro-Par, 1999)

A Morphological Approach to Hough Transform on an Instruction Systolic Array. - Bertil Schmidt; Manfred Schimmler; Heiko Schröder 001 (Comput. Artif. Intell., 1999)

Architectures and Algorithms for Multimedia Applications. - Manfred Schimmler (Euro-Par, 2000)

KPROC - An Instruction Systolic Architecture for Parallel Prefix Applications. - Bertil Schmidt; Manfred Schimmler (Parallel Distributed Comput. Pract., 2000)

Scanning Biosequence Databases on a Hybrid Parallel Architecture. - Bertil Schmidt; Heiko Schröder 001; Manfred Schimmler (Euro-Par, 2001)

Protein Sequence Comparison on the Instruction Systolic Array. - Bertil Schmidt; Heiko Schröder 001; Manfred Schimmler (PaCT, 2001)

Tomographic Image Reconstruction on the Instruction Systolic Array. - Bertil Schmidt; Heiko Schröder 001; Manfred Schimmler (Comput. Artif. Intell., 2001)

Massively Parallel Solutions for Molecular Sequence Analysis. - Bertil Schmidt; Heiko Schröder 001; Manfred Schimmler (IPDPS, 2002)

A hybrid architecture for bioinformatics. - Bertil Schmidt; Heiko Schröder 001; Manfred Schimmler (Future Gener. Comput. Syst., 2002)

Area and Time Efficient Modular Multiplication of Large Integers. - Viktor Bunimov; Manfred Schimmler (ASAP, 2003)

Key Generation for Secure High Speed Communication. - Viktor Bunimov; Manfred Schimmler; Wolfgang Bziuk (Security and Management, 2003)

Efficient Parallel Multiplication Algorithm for Large Integres. - Viktor Bunimov; Manfred Schimmler (Euro-Par, 2003)

Design of a Bit-Serial Floating Point Unit for a Fine Grained Parallel Processor Array. - Manfred Schimmler; Bertil Schmidt; Hans-Werner Lang (PDPTA, 2003)

A Simple Circuit to Reduce the Search Range for Large Prime Numbers. - Manfred Schimmler; Viktor Bunimov (VLSI, 2003)

An Area-Efficient Bit-Serial Integer Multiplier. - Manfred Schimmler; Bertil Schmidt; Hans-Werner Lang; Sven Heithecker (VLSI, 2003)

High Radix Modular Multiplication of Large Integers Optimised with Respect to Area and Time. - Viktor Bunimov; Manfred Schimmler (ESA/VLSI, 2004)

Fast Modular Multiplication by Operand Changing. - Manfred Schimmler; Viktor Bunimov (ITCC (2), 2004)

A bit-serial floating-point unit for a massively parallel system on a chip. - Manfred Schimmler; Bertil Schmidt; Hans-Werner Lang (Parallel Algorithms Appl., 2004)

Completely Redundant Modular Exponentiation by Operand Changing. - Viktor Bunimov; Manfred Schimmler (CDES, 2005)

Efficient Hardware Architectures for Modular Multiplication on FPGAs. - David Narh Amanor; Viktor Bunimov; Christof Paar; Jan Pelzl; Manfred Schimmler (FPL, 2005)

Hardware Enhanced Biosequence Alignment. - Gerd Pfeiffer; Heinz Kreft; Manfred Schimmler (METMBS, 2005)

A Configuration Concept for a Massively Parallel FPGA Architecture. - Sandeep S. Kumar; Christof Paar; Jan Pelzl; Gerd Pfeiffer; Manfred Schimmler (CDES, 2006)

Breaking Ciphers with COPACOBANA - A Cost-Optimized Parallel Code Breaker. - Sandeep S. Kumar; Christof Paar; Jan Pelzl; Gerd Pfeiffer; Manfred Schimmler (CHES, 2006)

COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking. - Sandeep S. Kumar; Christof Paar; Jan Pelzl; Gerd Pfeiffer; Manfred Schimmler (FCCM, 2006)

PLUG: An Agent Based Prototype Validation of CAD-Constructions. - Stefan Baumgart; Begona Toledo; Karin Spors; Manfred Schimmler (IKE, 2006)

Parallel Computing with Low-Cost FPGAs: A Framework for COPACOBANA. - Tim Güneysu; Christof Paar; Jan Pelzl; Gerd Pfeiffer; Manfred Schimmler; Christian Schleiffer (PARCO, 2007)

BMA - Boolean Matrices as Model for Motif Kernels. - Jan Schröder; Manfred Schimmler; Heiko Schröder 001; Karsten Tischer (BCBGC, 2008)

A Specification Methodology for the Optimal Layout of a 2-Stage Interconnect Bus for Massively Parallel Architectures. - Gerd Pfeiffer; Manfred Schimmler (CDES, 2008)

Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis. - Tim Güneysu; Christof Paar; Gerd Pfeiffer; Manfred Schimmler (FPL, 2008)

Massively Parallelized DNA Motif Search on the Reconfigurable Hardware Platform COPACOBANA. - Jan Schröder; Lars Wienbrandt; Gerd Pfeiffer; Manfred Schimmler (PRIB, 2008)

A Massively Parallel Architecture for Bioinformatics. - Gerd Pfeiffer; Stefan Baumgart; Jan Schröder; Manfred Schimmler (ICCS (1), 2009)

Collecting Statistical Information in DNA Sequences for the Detection of Special Motifs. - Lars Wienbrandt; Manfred Schimmler (BIOCOMP, 2010)

Using the reconfigurable massively parallel architecture COPACOBANA 5000 for applications in bioinformatics. - Lars Wienbrandt; Stefan Baumgart; Jost Bissel; Carol May Yen Yeo; Manfred Schimmler (ICCS, 2010)

MPI Performance Analysis of Amazon EC2 Cloud Services for High Performance Computing. - Florian Schatz; Sven Koschnicke; Niklas Paulsen; Christoph Starke 001; Manfred Schimmler (ACC (1), 2011)

Massively parallel FPGA-based implementation of BLASTp with the two-hit method. - Lars Wienbrandt; Stefan Baumgart; Jost Bissel; Florian Schatz; Manfred Schimmler (ICCS, 2011)

Dictionary Attack on TrueCrypt with RIVYERA S3-5000. - Ayman Abbas; Claas Anders Rathje; Lars Wienbrandt; Manfred Schimmler (ICPADS, 2012)

Improvement of BLASTp on the FPGA-Based High-Performance Computer RIVYERA. - Lars Wienbrandt; Daniel Siebert; Manfred Schimmler (ISBRA, 2012)

Optimizing Investment Strategies with the Reconfigurable Hardware Platform RIVYERA. - Christoph Starke 001; Vasco Grossmann; Lars Wienbrandt; Sven Koschnicke; John Carstens; Manfred Schimmler (Int. J. Reconfigurable Comput., 2012)

Master/Slave assignment optimization for high performance computing in an EC2 cloud using MPI. - Florian Schatz; Sven Koschnicke; Niklas Paulsen; Manfred Schimmler (Netw. Protoc. Algorithms, 2012)

An FPGA Implementation of an Investment Strategy Processor. - Christoph Starke 001; Vasco Grossmann; Lars Wienbrandt; Manfred Schimmler (ICCS, 2012)

Quality and consistency assurance of quote data for algorithmic trading strategies. - Sven Koschnicke; Vasco Grossmann; Christoph Starke 001; Manfred Schimmler (CIFEr, 2014)

FPGA-based Acceleration of Detecting Statistical Epistasis in GWAS. - Lars Wienbrandt; Jan Christian Kässens; Jorge González-Domínguez; Bertil Schmidt; David Ellinghaus; Manfred Schimmler (ICCS, 2014)

An efficient implementation of PBKDF2 with RIPEMD-160 on multiple FPGAs. - Ayman Abbas; Rian Voss; Lars Wienbrandt; Manfred Schimmler (ICPADS, 2014)

High-speed exhaustive 3-locus interaction epistasis analysis on FPGAs. - Jan Christian Kässens; Lars Wienbrandt; Jorge González-Domínguez; Bertil Schmidt; Manfred Schimmler (J. Comput. Sci., 2015)

Parallelizing Epistasis Detection in GWAS on FPGA and GPU-Accelerated Computing Systems. - Jorge González-Domínguez; Lars Wienbrandt; Jan Christian Kässens; David Ellinghaus; Manfred Schimmler; Bertil Schmidt (IEEE ACM Trans. Comput. Biol. Bioinform., 2015)

Combining GPU and FPGA technology for efficient exhaustive interaction analysis in GWAS. - Jan Christian Kässens; Lars Wienbrandt; Manfred Schimmler; Jorge González-Domínguez; Bertil Schmidt (ASAP, 2016)

Portfolio-based contract selection in commodity futures markets. - Vasco Grossmann; Manfred Schimmler (SSCI, 2016)

GPGPU-based identification of cointegrated portfolios. - Vasco Grossmann; Manfred Schimmler (SSCI, 2017)