Coupled variable-input LCG and clock divider-based large period pseudo-random bit generator on FPGA. - Mangal Deep Gupta; Rajeev K. Chauhan (IET Comput. Digit. Tech., 2021)

Secure image encryption scheme using 4D-Hyperchaotic systems based reconfigurable pseudo-random number generator and S-Box. - Mangal Deep Gupta; Rajeev K. Chauhan (Integr., 2021)

Efficient Hardware Implementation of Pseudo-Random Bit Generator Using Dual-CLCG Method. - Mangal Deep Gupta; Rajeev K. Chauhan (J. Circuits Syst. Comput., 2021)

Interference management in backhaul constrained 5G HetNets through coordinated multipoint. - Sandeep Gulia; Anwar Ahmad; Sandeep Singh; Mangal Deep Gupta (Comput. Electr. Eng., 2022)

Hardware Efficient Pseudo-Random Number Generator Using Chen Chaotic System on FPGA. - Mangal Deep Gupta; Rajeev K. Chauhan (J. Circuits Syst. Comput., 2022)

Hardware Efficient Hybrid Pseudo-Random Bit Generator Using Coupled-LCG and Multistage LFSR with Clock Gating Network. - Mangal Deep Gupta; Rajeev K. Chauhan; Sandeep Gulia (J. Circuits Syst. Comput., 2023)

Reconfigurable Image Confusion Scheme Using Large Period Pseudorandom Bit Generator Based on Coupled-Variable Input LCG and Clock Divider. - Mangal Deep Gupta; Rajeev K. Chauhan (J. Circuits Syst. Comput., 2024)