A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2) latch and its application in a dual-modulus prescaler. - Hongyan Yan; Manish Biyani; Kenneth K. O (IEEE J. Solid State Circuits, 1999)

An embedded 32-b microprocessor core for low-power and high-performance applications. - Lawrence T. Clark; Eric J. Hoffman; Jay B. Miller; Manish Biyani; Yuyun Liao; Stephen J. Strazdus; Michael Morrow; Kimberley E. Velarde; Mark A. Yarch (IEEE J. Solid State Circuits, 2001)

Low standby power state storage for sub-130-nm technologies. - Lawrence T. Clark; Franco Ricci; Manish Biyani (IEEE J. Solid State Circuits, 2005)

DEP-On-Go for Simultaneous Sensing of Multiple Heavy Metals Pollutants in Environmental Samples. - Madhu Biyani; Radhika Biyani; Tomoko Tsuchihashi; Yuzuru Takamura; Hiromi Ushijima; Eiichi Tamiya; Manish Biyani (Sensors, 2017)